Zenith Z-100 PC series Service Manual page 101

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Page
4-15
Detailed Circuit Description
As bus controller, the gate array decodes the status signals (SO, Sl, and
S2) from the microprocessor to provide the latching and enabling signal
for the buffers and address latches, as well as read/write signals for the
system memory and I/O devices.
As DMA controller, the gate array can transfer blocks of data from
memory to peripheral device, or vice versa, more rapidly and easily than
the microprocessor. This is possible because the gate array has its
instructions built in, and therefore does not need to decode them before
performing a data transfer operation. This also leaves the microproc­
essor free to perform other operations during data transfer, as long as
the busses are not needed.
When a data transfer is to be performed, a DREQ signal is sent to the gate
array. The gate array then assumes control of the busses from the
microprocessor long enough for the data transfer to be performed under
DMA control. Buffers allow the gate array to place its signals on the
busses only when the busses are under DMA control. During the data
transfer, the gate array generates its own address signals (AO through
A 19). Refer to Table 4-6 for a description of all gate array signals.
Table 4-6: Gate Array Signals
PIN SIGNAL
NUMBER NAME DESCRIPTION
VSS Ground.
2 TMR2 OUT2 from programmable
timer (U240). Refer to pin 68.
interval
3 TCLK Clock input to programmable inte
timer (U240).
rval
4 PBO Enables counter 2 of
interval timer (U240).
programmable
5 READY Ready signal
8087-2 (U234).
to 8088-2 (U235) and
6 NMI Non-maskable
8088-2.
interrupt signal to
INT87
INT signal from 8087-2 (U234). 7