Zenith Z-100 PC series Service Manual page 103

Page
4-17
Detailed Circuit Description
Table 4-6 (continued):
PIN SIGNAL
NUMBER NAME
32 RST*
33
VDD
34 ROW
35 VSS
36
BALE
37 CLKG
38 T/C*
39 MEMR
40 MEMW
41 lOR
42
MEM
43 KBDD
44
KBDC
Gate Array Signals
DESCRIPTION
Reset signal, including keyboard reset
(K YBRST*), 8088-2/8087-2 reset
(RESET), and the hex D flip-flop
(U256) that drives the CPU/memory
card LEDs.
+5VDC.
ROW signal to SB input (pin 1) of quad
multiplexers (U228 and U230) and to
pin 11 of address decoder (U231).
Ground.
Not connected.
Clock signal to 8088-2/8087-2 and to
buffer/driver (U246).
This signal when low indicates termi ­
nal count during DMA.
Memory read signal to pin 8 of octal
buffer (U252).
Memory write signal to pin 11 of octal
buffer (U252).
I/O read signal to pin 13 of octal
buffer (U252).
Indicates memory operation.
Data signal from keyboard.
Clock signal from keyboard.