Zenith Z-100 PC series Service Manual page 92

Page
4-6
Detailed Circuit Description
If the interrupt is a non-maskable interrupt, the microprocessor is
directed to the fixed address 008H. In all cases, a non-maskable interrupt
has priority over a maskable interrupt. If both types of interrupts occur
at the same time, the non-maskable interrupt will be processed first.
Non-maskable interrupts must also end with return (RET) commands.
System Timing
Figures 4-2 through 4-5 illustrate the timing for memory read, memory
write, I/O read, and I/O write operations, respectively. These diagrams
represent state changes in the signals listed in Table 4-3.
Table 4-3: Timing Signal Locations
LOCATION SIGNAL
Gate Array
pin 8 S2* ~
pin 9 Sl*
.'
pin 10
SO*
pin 37 CLKG
U236
pin 6
ALEB
U244
pin 1
DT/R*
pins 2 - 9 DO-D7
pin 19 GM*
U249
pins 2,5,6,9,12,15,16,19
AO-A7
U252
pin 7 IOR*
pin 16 IOW*
RAM
MW*
MAO-MA7
RAS*
CAS*
U238
pin 15
GCPU
The four states of each bus cycle are represented by the numbers T 1
thourgh T4 on the clock waveform in Figures 4-2 through 4-5. TW
represents a wait state.
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