Zenith Z-100 PC series Service Manual page 253

Page
3.6
Circuit Description
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When pin 39 of U305 is high, the SEEK signal is active and forces
the output at pin 1 of U306 low, indicating to the floppy controller
that it is seeking on a two-sided disk. The head within the drive can
be
moved in either of 2 directions. The SEEK signal enables pin 3
of NAND gate U306 which buffers and inverts the head direction con ­
trol signal (DIR) from pin 38 of U305. The status of the DIR* signal
determines which direction the head will be moved and is interfaced
to the disk drive through pin 18 of connector P301.
In the read/write mode pin 39 of U305 is low, driving pins 3 and 6
of U306 high which disable the head stepping and direction control
signals. The head within the disk drive therefore remains on that track
allowing data to be either written to or read from that track.
• Head Stepping - A stepping pulse is used to move the head within
the floppy drive to a different track. The SEEK signal enables pin 6
of NAND gate U306 which buffers and inverts the stepping pulse signal
(STP) from pin 37 of U305. The STP* signal is interfaced to the disk
drive through pin 20 of connector P301. After the head is stepped
to a different track and encounters track 0, the TRACKO* Signal be ­
comes active-low and forces pin 4 of U301 high, indicating to the floppy
controller that track 0 has been found.
• Write Data - Write data is converted from parallel to serial form by
the Floppy Disk Controller (FDC), buffered, and synchronized with the
Write Gate* signal by external logic.
The Write Enable (WE) signal from pin 25 of floppy controller U305
is buffered and inverted by pin 3 of three-state buffer U308. The result­
ing WRITE GATE* signal is interfaced to the disk drive through pin
24 of connector P301 , and enables the drive to accept data.
Data is written onto the disk at a rate determined by the WCK clock
frequency. The ripple carry output signal at pin 15 of U317 is paralleled
with pin 9 of OR gate U320 and pin 3 of flip-flop U315. The flip-flop
delays the signal and provides inputs to pin 10 of OR gate U320 and
pin 4 of flip-flop U315. The output at pin 8 of U320 is used to provide
the WCK clock signals which govern the Write Data transmission rate.
A high Signal at pin 5 of U315 enables pin 3 of U310 to transfer Write
Data.
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