Zenith Z-100 PC series Service Manual page 285

Page
3.38
Circuit Description
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Table 3.16. Backplane 1/0 Bus Signal Names
PIN
SIGNAL DEFINITION
A2-A9 D7-DO
Data bit 7 through Data bit O.
A10 I/OCHRDY liD Channel Ready. Used by slower liD devices to
ensure data is not lost during read and write opera ­
tions. May be held low (not ready) up to 10 clock cycles
(210 ns).
A11 AEN
Address Enable. Assigns control of read and write op­
erations to DMA controller.
A12-A31 A19-AO
Address bit 19 through address bit O.
B1 GND
Ground.
B2
RESET When high, resets, or initializes system logic devices.
B3
+5VDC +5 VDCbus.
B4
IRQ2
Interrupt Request 2. Not used but available for assign-
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ment to a user- selected device.
B6 DRQ2
DMA Request 2. Assigned to floppy disk controller.
B7
-12VDC -12VDCbus.
B9 +12VDC
+12VDCbus.
B10
GND Ground.
B11
MEMW*
Memory Write. When low, causes data on data bus
to be stored in memory.
B12
MEMR*
Memory Read. When low, causes memory to drive
data onto the data bus.
B13
10W* liD Write. When low, instructs an liD device to read
date on the data bus.