Zenith Z-100 PC series Service Manual page 286

Page
3.39
Circuit Description
Table 3.16 (continued). Backplane
I/O
Bus Signal Names
PIN SIGNAL DEFINITION
814 10R* I/O Read. When low, instructs an I/O device to drive
its data onto the data bus.
819 DACKO* DMA Acknowledge O. Assigned for timer number 1.
Initiates memory refresh cycle.
820 ClK 4.77 MHz system clock.
821
IR07*
Interrupt Request 7. Assigned to parallel interface.
822
IR06*
Interrupt Request 6. Assigned to floppy disk controller.
823 IR05* Interrupt Request 5. Assigned to Winchester drive con ­
troller.
824
IR04*
Interrupt Request 4. Assigned to serial port #1 (fixed).
825
IR03*
Interrupt Request 3. Assigned to serial port #2 (con ­
figurable).
826
DACK2*
DMA Acknowledge 2. Assigned to floppy disk control ­
ler.
827
T/C Terminal Count. Goes high when terminal count for
any DMA channel is reached.
829
+5VDC +5VDCbus.
830 OSC A 14.31818 MHz oscillator provides the basic timing
for the system.
831 GND Ground.