Zenith Z-100 PC series Service Manual page 95

Page
4-9
Detailed Circuit Description
T3
8MHz
INVAllO 1 ClK CYCLE
AlEB
t
FROM HERE
AO-A8
I
1
"'10ns
~40ns
IOR*----------------'1
I --­
1~~~2~0-n-s------------------------------------------------~ 1~30ns
00-07 - - - - - - - - - ' 1 1 ____ .
r--------------------------------------------
~~50ns
GCPU------------------------~ LI~
__- ­
GM* 1---,6ons
I
OT/R*-------------------------------------------------------------­
5MHz
I
80*-82* 4-I40170nS
1~~f~0~n-s~--~I~i~2~0-n-S----------------~----
______________
- J
AlEB
1~40nS
AO-A8
I
I
I OR* _ _ _ _ _ _ _--, ~,.8-0-n s;..-.__
~I~
_____
------------~I
1,..20ns
00-07-----------------
I
l:::=:a
90ns
I
G CPU
----------------------~
I
~."_1
, ; ;, O , ; ;, O ;, ; . n
s~
__
L -______________________ -J
GM* ----------------------.
r"r
OT/R*------------------------------------------------------------- ­
NOTE: 80*-82* at gate array; IOR* at U46; AO-A8 at U40; ClKG, AlEB, GM* , 00-07, and OT/R* at U51
Figure 4-4: I/O Read Timing