Zenith Z-100 PC series Service Manual page 76

IV
Contents
Figures
2-1 Switch and Jumper Locations .2-1
3-1
CPU/Memory Card Block Diagram .3-1
4-1 8088-2 Microprocessor Pinouts .4-1
4-2 Memory Read Timing .4-7
4-3 Memory Write Timing . . . . . .4-8
4-4
I/O Read Timing . . . . . . . . .4-9
4-5 I/O Write Timing . . . . . . . . . . . . .4-10
4-6
Programmable Interval Timer Pinouts .4-12
4-7 Interrupt Controller Pinouts .4-13
4-8 Gate Array Pinouts . . . . . . .4-14
4-9 Peripheral Connector Pinouts .4-19
4-10
Keyboard Connector Pinouts .4-21
5-1
Backplane Board Power Supply LEDs .5-2
5-2
CPU /Memory Card LEDs . . . . . . . . . . . . . . . . . . . . .5-3
6-1
CPU/Memory Card Component Layout . . . . . . . . . . . .6-1
6-2
CPU Schematic . . . . . .6-12
6-3 Parallel Port Schematic .6-13
6-4
Memory Schematic . . . .6-14
6-5 Gate Array Control Schematic .6-15
6-6
Gate Array DMA Schematic .6-16
Tables
2-1 CPU Clock Frequency Selection .2-2
2-2 SW202 Settings . . . . . . . . . .
.2-2
2-3 Jumpers J202 and J203 Settings .2-4
2-4 Jumpers J204, J205, and J206 Settings .2-5
4-1 8088-2 Microprocessor Signals
.4-2
4-2 SO, SI, and S2 Signal Decoding
.4-5
4-3 Timing Signal Locations
.4-6
4-4 Programmable Interval Timer Operating Modes
.4-11
4-5 Programmable Interval Timer Programming Codes
.4-12
4-6 Gate Array Signals . . . . . .
.4-15
4-7 Peripheral Connector Signals . . . . . . . . . . . . .
.4-20
4-8 Keyboard Signals . . . . . . . . . . . . . . . . . . . .
.4-21
5-1 Error Messages . . . . . . . . .
.5-4
6-1 CPU/Memory Card Parts List
. . . . . . . . . . . . . . . . . .6-2
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