Zenith Z-100 PC series Service Manual page 91

Page
4-5
Detailed Circuit Description
The rest of the instruction cycle is determined by the conten t of the
instruction. It may involve memory reads or writes, or internal
processing which does not generate external signals. Address outputs A8
through A 19 are processed the same as ADO through AD7. Instruction
cycles involving I/O devices are identical to operations involving
memory, except for the state of signals SO, SI, and S2, as shown in Table
4-2.
Table 4-2: SO, S1, and S2 Signal Decoding
SO SI S2
STATE STATE STATE FUNCTION
Low Low Low Interrupt acknowledge
Low Low High
Read I/O port
Low High Low Write I/O port
Low High High
Halt
High
Low Low Code access
High Low High Read memory
High High
Low Write memory
High High High Idle
Interrupt Operation
There are two types of interrupts used with the 8088-2. The non­
maskable interrupt (NMI) cannot be ignored by the device, while some
instructions can tell the microprocessor to ignore maskable interrupts
(lNTR). In either case, the basic operation of the interrupt is the same.
When a maskable interrupt occurs, the interrupting device sends an 8-bit
type number to the interrupt controller (U241), which prioritizes up to
eight interrupt inputs at one time. The interrupt controller then sends an
INTR signal to microprocessor at pin 18 to notify it of a waiting
interrupt.
When the interrupt is acknowledged, the interrupt controller points to
the location where the address of the interrupt routine is stored. As many
as 64 different devices can be handled by cascading the interrupt
controllers.
The microprocessor will then execute the first instruction found at that
address. The interrupt program must end with a return command (RET),
which causes the 8088-2 to return to the operation which was
interrupted.