Zenith Z-100 PC series Service Manual page 260

Page
3.13
Circuit Description
1 - - - - - ( R 0) - 1
- - - - - I
1 - - - -
(R 2 ) - 1
-------I
1 - - - (R 1)
- - - I
DISPEN
HSYNC
Figure
3.3.
Horizontal Timing and Format
• Vertical Timing and Format Registers - Registers R4 through R9
are normally loaded at system startup and normally are not changed
thereafter. The point of reference for these registers is the top-most
character position displayed on the monitor screen.
The vertical total register, R4, and the vertical sync adjust register
determine the total number of scan line times in a frame, including
vertical retrace, establishing the overall frame rate or VSYNC fre ­
quency.
R4 is a 7-bit register loaded with the total number of character rows.
Since a character row can consist of up to 32 scan lines, it may be
difficult to establish a refresh frequency close to the line frequency.
Register R5, a 5-bit VSYNC adjust register, then may be used to fine­
tune the VSYNC frequency. R5 is loaded with a value representing
scan line times.
The character-rows-displayed register, R6, is a 7-bit register which
allows the selection of the number of rows of characters to be dis­
played, up to 128. What is specified for this register does not determine
the positions of the VSYNC pulse, but the pOint at which display enable
(DIS PEN) will be reset for vertical retrace.
R7, the vertical sync (VSYNC) position register, determines the pOint
at which the VSYNC signal makes its negative-to-positive transition
to initiate vertical retrace. VSYNC position is determined by the charac­
ter row time, measured from the first character row on the monitor