Zenith Z-100 PC series Service Manual page 276

Page
3.29
Circuit Description
Table 3.11. Gate Array
1/0
Signal Description and Pinouts
PIN NUMBER SIGNAL NAME DESCRIPTION
30
BCLK
Control/timing signals to CRTC.
31 RDNW Enables READ when high, WRITE
when low.
32 ECLK Enables CRTC I/O drivers, and used
to clock data in and out of CRTC.
33 NRDY Activates "I/O CHIP READY" signal.
36 RASD·
Select 0 (SO) input to video
RAM address multiplexers.
37 CPU Select 0 (SO) input to video RAM
address multiplexers, enables
memory WRITE operation.
38 TO Video RAM address multiplexer input.
39 T1 Video RAM address multiplexer input.
40,41,42 R1, G1, B1 RGB serial data.
43 11 "INTENSITY" bit.
44
V1 Vertical sync output from gate array.
45 H1
Horizontal sync from gate array.
46 NIOW I/O WRITE enable.
47
MRD·
Memory READ enable.
48 NIOR I/O READ enable.
49 RESET· Resets CRTC and U336.
50 OSC
Clock input to gate array.
53 VSEL Video select output.