Zenith Z-100 PC series Service Manual page 256

Page
3.9
Circuit Description
Table 3.1.
SIGNAL
AOtoA19
DOtoD7
CS"
RS
RIW"
E
ClK
RESET"
Vcc(+5 V)
andVss
(Ground)
Video Logic-to-System Logic Interface Signals
FUNCTION
The 20 system address lines used to access memory locations.
Bidirectional data lines which transfer information between the
CPU and the internal registers of the 6845.
Chip Select signal typically generated by system address decoding
logic. CS" must be low to read information from, or write informa­
tion to, one of the 6845 internal registers.
6845 register select signal. Rather than sacrifice five of the
40
available pins to 6845 register-addressing, one of the registers
is used as an address register to access the other 18 registers.
When the RS signal is low, the address register is accessed and
then can be loaded with the address of the internal register to
be accessed next. When RS is high, the address9d register may
be accessed.
The read/write Signal. It determines whether data is to be written
into or read from an internal register. RIW" is low for a write opera­
tion, high for a read operation.
The enabling (synchronizing clock) signal required by the 6845
which enables the internal I/O buffers and clocks data into and
out of the internal registers via the data buffers. In this computer,
the E input connects to the gate array.
Synchronizes the 6845's control signals. It is derived from the sys­
tem clock to become the character rate clock in text mode. Al­
though this signal is more closely related to the character generator
and video interface, it is included here because it is the primary
timing unit to the 6845.
Initializes the 6845. When this pin goes low, the internal counters
are cleared and the 6845 outputs go low, effectively stopping the
video display operation. As the RESEr signal does not affect
the program-accessible counters within the 6845, display may con­
tinue when RESET" goes high.
Standard TTL power levels which enable proper operation of the
ICs.