Zenith Z-100 PC series Service Manual page 105

Page
4-19
Detailed Circuit Description
Table 4-6 (continued): Gate Array Signals
PIN SIGNAL
NUMBER NAME DESCRIPTION
62 PARITY Parity bit for DIN inputs (pin 2) of
RAM devices U201, U210,and U219.
63 CPUGA* Input to enable the I/O addresses in
the gate array.
64 AENI When high during DMA cycles, this
signal disables the address drivers of
the CPu.
65
DEN Data enable signal to DEN input (pin
13) of gate array control (U238).
66
IRQl Interrupt request signal to IR 1 (pin 19)
input of interrupt controller (U24
1).
67
VDD +5VDC.
68
TMRI OUTI from programmable interval
timer (U240). Refer to pin 2.
Peripheral Interface
Table 4-7 identifies the signals at the parallel port on the CPU/memory
card. Refer to Figure 4-9 for the connector pinouts.
Figure 4-9: Peripheral Connector Pinouts