Zenith Z-100 PC series Service Manual page 102

Page
4-16
Detailed Circuit Description
")
Table 4-6 (continued): Gate Array Signals
PIN SIGNAL
NUMBER NAME
8 - 10 SO* - S2*
11 DT/R*
12 - 17 AO - A3, A5, A 7
18 - 20 BDO - BD2
21 - 22 DREQ2 - DREQ3
23 I/OCHRDY
24 DREQI
25
I/OCHCHK*
26 - 28
LDO-LD2
29 DMA*
30
INTA*
31 lOW
DESCRIPTION
SO*, SI*, and S2* signals from 8088-2
(U235) and/or 8087-2 (U234). Refer to
Table 4-2.
Signal specifying transmit or receive
status to data transceiver (U245).
Address inputs.
Data outputs (refer also to pins 56 ­
60).
Request for DMA channels 2 and 3
(refer also to pin 24).
I/O CH ready signal from bus.
Request for DMA channell (refer also
to pins 21 and 22).
I/O CH check signal from bus.
Signals to load data into 8-bit latches
U249, U250 and U255 respectively.
Signal to enable the outputs of 8-bit
latches U249 and U250.
Interrupt acknowledge signal to in­
terrupt controller U241.
I/O write signal to gate array control
(U238) and bus (IOW*), and to decoder
(U253).