Zenith Z-100 PC series Service Manual page 254

Page
3.7
Circuit Description
• Write Precompensation - The Write Data (WDA) output from pin 30
of U305 is applied to the write precompensation circuitry consisting
of flip-flop U315, the three NAND gates of U31 0, and multiplexer U314.
The PSO and PS1 inputs to U314 are used to determine early, late,
and nominal precompensation status. See the following Precompensa ­
tion Chart.
PSO PS1
Normal 0
0
Late
0
1
Early 1 0
Invalid 1
1
When the status is nominal, the WDA is output at pin 9 of U314,
fed back to flip-flop U315, and then output as the WRTDATA signal.
Pin 4 of U307 buffers and inverts the WRTDATA signal providing the
WRTDATA* signal which is interfaced to the disk drive through pin
22 of connector P301.
• Write Protection - During the write cycle, pin 39 of U305 is in a
low state, enabling pin 11 of NOR gate U306. If the disk being used
has a write protect tab on it, a low signal will result at pin 12 of NOR
gate U306. The output at pin 11 of U306 therefore goes high indicating
to the floppy controller that the disk in use cannot be written to.
During the write cycle, the low signal at pin 39 of U305 disables pins
3 and 6 of NAND gates U306 so that the direction (DIR) and stepping
pulse (STEP) signals cannot affect the read/write head in the disk
drive.
• Read Data - During the read cycle, data is interfaced to the Color
Video/ Floppy Controller Card through pin 30 of connector P301. The
serial signals are applied to data separation chip U304 which separates
the serial clock signals from data signals as they are received from
a floppy drive. U304 is active on the leading edge of a pulse and
has a reference clock input of approximately 4 MHz derived from pin