Zenith Z-100 PC series Service Manual page 100

Page
4-14
Detailed Circuit Description
Gate Array
The gate array (U248) on the CPU/memory card has several different
functions, including signal generation, bus control, and DMA control.
Figure 4-8 illustrates the pinouts for the gate array and Table 4-6
identifies the signals.
>­
-~o:5~
2LL.Jo::lU2.
20::::a....1-1­
DREQ2
1/0 CH RDY 23
DREQI
Figure 4-8: Gate Array Pinouts
As signal generator, the gate array provides either a 4.77 MHz or 8.0 MHz
33% duty cycle clock signal (CLKG) to the 8088-2, as determined by the
position of switch SW201 (refer to Chapter 2). It also provides
synchronization for the RDY signal, and provides the RESET signal at
power-up. Additional timing signals (TCLK and CLK) are sent by the
gate array to the programmable interval timer (U240), and to the busses
to provide synchronization for other devices, by way of the buffer /dri­
ver (U246).