Zenith Z-100 PC series Service Manual page 275

Page
3.28
Circuit Description
Table 3.11. Gate Array 1/0 Signal Description and Pinouts
PIN NUMBER SIGNAL NAME DESCRIPTION
1,18,35,52 GND Ground.
2 LPIN Light Pen input.
3 VRAM*
Video RAM decode.
4 LPSW Light Pen Switch.
5 RAMG*
Enables U330 on RAM read cycle.
6 ROMG* Enables U328 on ROM read cycle.
7-14 GAO-GA7
8-bit onboard data bus.
15 CSGA* Chip Select for gate array.
,
~
16 NRFSH Enables RAM refresh cycle.
17,34,51,68
+5VDC Gate array power source.
19
CAS*
Column Address Strobe, high
during refresh cycle.
20
RAS* Row Address Strobe, active
signal that refreshes RAM.
21
RA1,2* NANDed Row Address bits 1 and 2
fromCRTC.
22 LPEN Strobe input to CRTC.
23 MA11 Memory Address bit 11 from CRTC.
24
MA12 Memory Address bit 12 from CRTC.
25
RAO Row Address bit 0 from CRTC.
26
VA11 Video RAM address multiplexer input.
27
VA12 Video RAM address multiplexer input.
28 VSYNC Vertical sync input from CRTC.
29 HSYNC
Horizontal sync input from CRTC.
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