Toshiba TECRA M9 Maintenance Manual page 72

2 Troubleshooting Procedures
Table 2-5 Serial port (Boot mode) error status (3/9)
D port
Status
F100h
Renewal of a microcode （Only
support model）
Prohibition of cache
Permission of L1/L2 cache in
FlashROM area
Initialization of H/W (before
DRAM recognition)
Initialization of PIT channel 1
F101h Check of DRAM type and size
(at cold boot)
SM-RAM stack area test
F102h Cache configuration
Cache permission(L1/L2 cache)
CMOS access test
(at cold boot)
Battery level check of CMOS
CMOS checksum check
Initialization of CMOS data (1)
Setting of IRT status
Storing DRAM size in CMOS
F103h Resume branch (at cold boot)
2-22
Test item
Initialization of MCH
Initialization of ICH6M D30.Func0
Initialization of ICH6M.D31.Func0
Initialization of ICH6M.D31.Func1/2
Initialization of USB Controller
Initialization of ICH6M.D31.Func3
Initialization of ICH6M AC97 Audio
Initialization of TI Controller
(Setting the refresh interval to "30μs")
When unsupported memory is connected, becoming
HLT after beep sound
HLT when DRAM size is 0
HLT When it can not be used as a stack
(HLT when an error is detected)
(Setting of boot status and IRT busy flag, The rest bits
are 0)
[CONFIDENTIAL]
2.4 System Board Troubleshooting
Message
Not resume when a CMOS error occurred
Not resume when resume status code is not set
Resume error check
S3 returning error (1CH) (Resume error LED=7AH)
SM-RAM checksum check (Resume error
LED=73H)
TECRA M9 Maintenance Manual (960-631)