Processor 7/7 - EUROCOM N150SC Service Manual

Processor 7/7

5
CFG STRAPS FOR PROCESSOR
D PCI EXPRESS STATIC LANE REVERSAL FOR ALL PEG PORTS
1: (DEFAULT)NORMAL OPERATION;
LANE# DEFINITION MATCHES
CFG2
SOCKET PIN MAP DEFINITION
0: LANE REVERSAL
CFG2 R78 *1K_04
DISPLAY PORT PRESENCE STRAP
1: DISABLED;
NO PHYSICAL DISPLAY PORT ATTACHED
TO EMBEDDED DISPLAY PORT
C 0: ENABLED;
CFG4
AN EXTERNAL DISPLAY PORT DEVICE
IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
CFG4 R70 1K_04
PCIE PORT BIFURCATION STRAPS
11: (Default) x16 - Device 1 functions 1 and 2 disabled
B
10: x8, x8 - Device 1 function 1 enabled ; function 2 disabled
CFG[6:5]
01: Reserved - (Device 1 function 1 disabled ; function 2 enabled)
00: x8,x4,x4 - Device 1 functions 1 and 2 enabled
CFG5 R77 *1K_04
CFG6 R68 *1K_04
DEFENSIVE PULL DOWN SITE
CFG7 1: (Default) PEG Train immediately following xxRESETB de assertion
0: PEG Wait for BIOS for training
A
CFG7 R69 *1K_04
5
4 3
Haswell Processor 7/7 ( RESERVED )
HASW ELL_BGA_E
U1K
F1
RSVD_TP
E1
RSVD_TP
RSVD_BE4
BE4 A5
RSVD_TP RSVD_TP
RSVD_BD3 BD3 A6
RSVD_TP RSVD_TP
RSVD_F6
F6 R54
RSVD_TP CFG_RCOMP
RSVD_A35
G6 Y52
RSVD_TP CFG16
V53
RSVD_G21 CFG18
G21 Y51
RSVD_G24 RSVD_TP CFG17
G24 V52
RSVD_TP CFG19
TESTLO_F21
F21
TESTLO_F21
G19 B50
VSS RSVD
F51 AH49
VSS RSVD
F52 AM48
VSS RSVD
F22 AU27
VCCIN
VCC RSVD
AU26
RSVD
RSVD_L52 L52 BD4
RSVD_L53 RSVD_TP RSVD
L53 BC4
RSVD_TP RSVD
AL6
RSVD
RSVD_L51
L51 F8
RSVD_TP RSVD
RSVD_F24
F24
RSVD_TP
RSVD_F25
F25
RSVD_TP
TESTLO_F20
F20
TESTLO_F20
CFG0 AG49 F16
CFG0 RSVD
CFG1 AD49
CFG1
CFG2 AC49
CFG2
AE49
CFG3
CFG3
CFG4 Y50
CFG4
CFG5 AB49
CFG5
R80 CFG6 V51 G12
CFG6 RSVD_TP
W51 G10
*1K_04 CFG7
CFG7 RSVD_TP
CFG8 Y49
CFG8
CFG9 Y54 H54
CFG9 VSS
CFG10 Y53 H53
CFG10 VSS
W53
CFG11
CFG11
CFG12 U53 H51
CFG12 VSS
CFG13 V54 H52
CFG13 VSS
CFG14 R53
CFG14
R52 N51
CFG15
CFG15 RSVD
G53
RSVD
L50 H50
RSVD RSVD
L49
RSVD
E5
RSVD
11 OF 12
TESTLO_F20
R30
TESTLO_F21
R29
CFG_RCOMP
R382
4 3
2 1
HASW ELL_BGA_E
U1L
RSVD_F1
RSVD_E1
RSVD_A5
RSVD_A6 A3
B3 TO A3
TP_A4 DAISY_CHAIN_NCTF_A3
A4
DAISY_CHAIN_NCTF_A4
CFG_RCOMP
CFG16
DAISY_CHAIN_NCTF_BF51
CFG17
TP_A51 DAISY_CHAIN_NCTF_BF52
CFG18 A51
DAISY_CHAIN_NCTF_A51 DAISY_CHAIN_NCTF_BF53
CFG19 A52 TO B52 A52
DAISY_CHAIN_NCTF_A52
A53 TO B53 A53
DAISY_CHAIN_NCTF_A53 DAISY_CHAIN_NCTF_C1
DAISY_CHAIN_NCTF_C2
DAISY_CHAIN_NCTF_C3
B2 TO C3 B2
DAISY_CHAIN_NCTF_B2
B3 TO A3 B3
DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_C54
DAISY_CHAIN_NCTF_D1
A52 TO B52 B52
DAISY_CHAIN_NCTF_B52
A53 TO B53 B53
DAISY_CHAIN_NCTF_B53 DAISY_CHAIN_NCTF_D54
B54 TO C54 B54
DAISY_CHAIN_NCTF_B54
TP_BC1
BC1
DAISY_CHAIN_NCTF_BC1
TP_BC54
BC54
DAISY_CHAIN_NCTF_BC54
BE1 TO BD1 BD1
DAISY_CHAIN_NCTF_BD1
BE54 TO BD54 BD54
DAISY_CHAIN_NCTF_BD54
BE1
BE1 TO BD1
DAISY_CHAIN_NCTF_BE1 RSVD
BF2 TO BE2 BE2
DAISY_CHAIN_NCTF_BE2 RSVD
BF3 TO BE3 BE3
DAISY_CHAIN_NCTF_BE3 RSVD
RSVD_G12
BF52 TO BE52 BE52
DAISY_CHAIN_NCTF_BE52 RSVD
BE53
BE53 TO BF53
DAISY_CHAIN_NCTF_BE53 RSVD
BE54 TO BD54 BE54
DAISY_CHAIN_NCTF_BE54 RSVD
BF2 TO BE2 BF2
DAISY_CHAIN_NCTF_BF2 RSVD
BF3 TO BE3 BF3
DAISY_CHAIN_NCTF_BF3 RSVD
TP_BF4 BF4
DAISY_CHAIN_NCTF_BF4
12 OF 12
49.9_1%_04
49.9_1%_04
49.9_1%_04
! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/ ! ! ! !!DMFWP!DP/
Title Title Title
[08] Haswell Processor 7/7 [08] Haswell Processor 7/7 [08] Haswell Processor 7/7
Size Size Size Document Number Document Number Document Number
6-71-N1500-D02A 6-71-N1500-D02A 6-71-N1500-D02A
[5,7,42] VCCIN Custom Custom Custom
Date: Date: Date: Tuesday, December 16, 2014 Tuesday, December 16, 2014 Tuesday, December 16, 2014
2 1
Schematic Diagrams
D
TP_BF51
BF51
BF52
BF52 TO BE52
BF53 BE53 TO BF53
C1 C1 TO C2
C2
C3 B2 TO C3
C54 B54 TO C54
TP_D1
D1
TP_D54
D54
Sheet 8 of 55
AN35
AN37 C
Processor 7/7
AF9
AE9
G14
G17
AD45
AG45
B
A
R e v R e v R e v
2.0A 2.0A 2.0A
Sheet Sheet Sheet 8 8 8 o f o f o f 55 55 55
Processor 7/7 B - 9