SOLTEK SL-75DRV3/75DRV3+ User Manual page 64

75DRV3/75DRV3+
* AGP Master 1 ws
* AGP Master 1 ws
CPU & PCI Bus Control
CMOS Setup Utility - Copyright (C) 1984-2001 Award Software
PCI1 Master 0 WS Writer
PCI2 Master 0 WS Write
PCI1 Post Write
PCI2 Post Write
PCI Delay Transaction
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
* PCI1 Master 0 WS
* PCI2 Master 0 WS
* PCI1 Post Write Leave this field at default.
* PCI2 Post Write Leave this field at default.
* PCI Delay Transac-
Leave this field at default.
write
Leave this field at default.
read
CPU & PCI Bus Control
Enabled
Enabled
Enabled
Enabled
Disabled
When Enabled, writes to the PCI bus are executed
Write with zero wait states.
The choice: Enabled, Disabled.
Leave this field at default.
Write
Leave this field at default.
tion
64
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