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75DRV3/75DRV3+
DRAM Clock/Drive Control
CMOS Setup Utility - Copyright (C) 1984-2001 Award Software
Current FSB Frequency
DRAM Clock
DRAM Timing
SDRAM Cycle Length
Bank Interleave
DRAM Command Rate
:Move Enter:Select +/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Fail-Safe Defaults F7:Optimized Defaults
* Current FSB Fre-
quency
* DRAM Clock The value represents the performance parameters
* DRAM Timing When this item Enabled, DRAM Timing is set by
* SDRAM Cycle Length Select CAS latency time in HCLKs of 2 or 3. The
* Bank Interleave The choices: Disabled; 2 Bank; 4 Bank.
* DRAM Command
DRAM Clock/Drive Control
100MHz
100MHz
By SPD
2.5
Disabled
1T Command
This item allows you to control the FSB Frequency.
of the installed memory chips (DRAM). Do not
change the value from the factory setting unless you
install new memory that has a different performance
rating.
SPD.
SPD (Serial Presence Detect) is located on the
memory modules, BIOS reads information coded in
SPD during system boot up.
system designer already set the values. Do not
change the default value unless you change speci-
fications of the installed DRAM or the installed CPU.
The choices: Disabled; 2 Bank; 4 Bank.
Rate
62
Item Help
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