IBM NeXtScale System Planning And Implementation Manual page 82

Such new tri-gate transistor technology enabled a new architecture with which
you can share data on-chip through a high-speed ring that is interconnected
between all processor cores, the last level cache (LLC), and the system agent.
The system agent houses the memory controller and a PCI Express root
complex that provides 40 PCIe 3.0 lanes.
The integrated memory controller in each CPU still supports four memory
channels with three DDR3 DIMMs per channel but now runs at a speed that is up
to 1866 MHz. Two QPI links still also connect to a second CPU in a dual-socket
installation.
The Xeon E5-2600 v2 series is available with up to 12 cores and 30 MB of
last-level cache. It features an enhanced instruction set that is called Intel
Advanced Vector Extensions (AVX). It doubles the operand size for vector
instructions (such as floating-point) to 256 bits and boosts selected applications
by up to a factor of two.
The implementation architecture includes Intel Turbo Boost Technology 2.0 and
improved power management capabilities. Turbo Boost automatically turns off
unused processor cores and increases the clock speed of the cores in use if
thermal requirements are still met. Turbo Boost Technology 2.0 uses the
integrated design and implements a more granular overclocking in 100 MHz
steps instead of 133 MHz steps on older microprocessors.
As with iDataPlex servers, NeXtScale servers support S3 mode. S3 allows
systems to come back into full production from low-power state much quicker
than a traditional power-on. In fact, cold boot normally takes about 270 seconds;
with S3, cold boot occurs in only 45 seconds. When you know a system will not
be used because of time of day or state of job flow, you can send it into a very
low-power state to save power and bring it back online quickly when needed.
Table 4-1 summarizes the differences between both Intel's micro architecture
implementations. Improvements are highlighted.
Table 4-1 Comparison between Xeon E5-2600 and Xeon E5-2600 v2
QPI Speed (GT/s)
Addressability
Cores
Threads per socket
Last-level Cache (LLC)
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IBM NeXtScale System Planning and Implementation Guide
Xeon E5-2600
(Sandy Bridge-EP)
8.0, 7.2 and 6.4 GT/s
46 bits physical, 48 bits virtual
Up to 8
Up to 16 threads
Up to 20 MB
Xeon E5-2600 v2
(Ivy Bridge-EP)
Up to 12
Up to 24 threads
Up to 30 MB