CHAPTER 3 THEORY OF OPERATION
1.2
Main PCB Block Diagram
Fig. 3-2 shows the block diagram of the main PCB.
Reset Circuit
Boot + Font ROM (8 MB)
Main Program (3 MB)
STRAGE (1 MB)
RAM (32 MB)
RAM (DIMM) (max. 128MB)
Compact
Flash
EEPROM (2048 x 8 bit)
To PC
or Hub
CPU Core
(SPARClite 200MHz)
BUS
Media Gate
Array
To Engine PCB
NC-6100h
Oscillator 66.6MHz
INT
Address Decoder
DRAM Control
CDCC Parallel I/O
Oscillator 12MHz
Soft Support
EEPROM I/O
Engine Control I/O
Fig. 3-2
3-2
A S I C
Timer
FIFO
USB I/O
AIO Control
To PC
To PC