1.2
Main PCB Block Diagram
<HL-720>
Fig. 2.3 shows a block diagram of the main PCB.
Reset Circuit
DRAM
0.5 Mbytes
Option RAM
1.5 Mbytes or
3.5 Mbytes
EEPROM
(128 x 8 bits)
Motor Driver
CPU Core
(Z80)
BUS
DRAM Control
To Panel sensor PCB
Fig. 2.3
II-3
ASIC
Oscillator
(12.27 MHz)
INT
Program ROM
16 Kbytes
Working S-RAM
512 Bytes
Timer
CDCC
Parallel I/O
DATA
Extension
FIFO
EEPROM I/O
Engine
Control I/O
To PC
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