CHAPTER 3 THEORY OF OPERATION
1.2
Main PCB Block Diagram
Fig. 3-2 shows the block diagram of the main PCB. (HL-5130/5140/5150D/5170DN)
Reset Circuit
Program + Font ROM
HL-5130:2MB
HL-5140:4MB
HL-5150D/5170DN:8MB
Network Program
(HL-5170DN only)(1.5 MB)
STRAGE (0.5 MB)
RAM
HL-5130:8MB
HL-5140/5150D:16MB
HL-5170DN:32MB
RAM (DIMM)
(max. 128MB)
Option for HL-5140/5150D/5170DN
EEPROM
HL-5130/5140/5150D:512 x 8 bit
HL-5170DN:8192 x 8 bit
To PC
or Hub
CPU Core
(SPARClite 133MHz)
BUS
To Engine PCB
Network Controller
(HL-5170DN only)
Oscillator 25MHz
(HL-5170DN only)
Oscillator 66.6MHz
INT
Address Decoder
DRAM Control
CDCC Parallel I/O
Oscillator 12MHz
EEPROM I/O
Engine Control I/O
PCI Bus Control
Fig. 3-2
3-2
A S I C
Timer
FIFO
USB I/O
Soft Support
To PC
To PC