Component Overview; Cpu; Memory Subsystem; I/O Bridge Chip - Sun Microsystems Ultra 25 Service Manual

C.1.3

Component Overview

This section describes some primary motherboard components.
C.1.3.1

CPU

UltraSPARC IIIi 1.6-GHz CPU for the Sun Ultra 45, UltraSPARC IIIi 1.34-GHz
CPU for the Sun Ultra 25.
Integrated L1 caches (data, instruction, prefetch, and write)
Integrated 1-Mbyte L2 data cache
System bus – I/O bridge, JBus frequency up to 200 MHz.
C.1.3.2

Memory Subsystem

Integrated DDR-1 SDRAM 266-MHz memory controller
Memory – up to eight DDR-1 SDRAM 266-MHz registered DIMMs, (four per
CPU) for the Sun Ultra 45, up to four DDR-1 SDRAM 266-MHz registered
DIMMs, (four per CPU) for the Sun Ultra 25.
16 GBytes for dual CPU, 8 GBytes of memory for single CPU
C.1.3.3

I/O Bridge Chip

Sun Microsystems I/O bridge ASIC
JBus
Dual PCI buses
C.1.3.4

I/O Subsystem

UltraDMA ATA 133 controller
AC-97 compliant audio interface
USB 2.x interface
C-4 Sun Ultra 45 and Ultra 25 Workstations Service and Diagnostics Manual • May 2006
200-MHz bandwidth
128-bit wide MUX address and data bus
PCI-X compliant
8 x 64-byte I/O cache each bus
Fully associative I/O memory management unit on each bus
PCI-E 2 long connector is 16 lane capable, running 8 lanes
PCI-E 1 long connector is 16 lane capable, running 8 lanes
PCI-E 0 short connector is 8 lane capable, running at 4 lanes