Advanced Chipset Features - ICP Electronics ROCKY-3786EV User Manual

4.7 Advanced Chipset Features

CMOS Setup Utility – Copyright © 1984 – 2000 Award
Advanced Chipset Features
SDRAM CAS Latency Time
SDRAM Cycle Time Tras/Trc
SDRAM RAS-to-CAS Delay
SDRAM RAS Precharge Time
System BIOS Cacheable
Video BIOS Cacheable
Memory Hole At 15M-16M
CPU Latency Timer
Delayed Transaction
AGP Graphics Aperture Size
System Memory Frequency
Power – Supply Type
Special NT4.0 DRAM Report
On-Chip VGA
↑↓←→Move Enter: Select
F1:General Help
F5:Previous Values
This section allows the user to configure the system based on
the specific features of the installed chipset.
manages bus speeds and access to system memory resources,
such as DRAM and the external cache.
communications between the conventional ISA bus and the PCI
bus. It must be stated that these items should never need to
be altered. The default settings have been chosen because they
provide the best operating conditions for the user's system.
DRAM Settings
The first chipset settings deal with CPU access to dynamic
random access memory (DRAM).
been carefully chosen and should only be altered if data is being
lost. Such a scenario might well occur if the user's system had
mixed speed DRAM chips installed so that greater delays may
Software
3
Auto
Auto
Auto
Disabled
Disabled
Disabled
Enabled
Enabled
64MB
Auto
ATX
Disabled
Enabled
+/-/PU/PD: Value
F6:Fail-safe defaults
The default timings have
Item Help
____________________
Menu Level
F10:Save ESC: Exit
F7:Optimized Defaults
This chipset
It also coordinates
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