Input Signals - Intel Itanium 2 Processor Datasheet

Signals Reference
Table A-12. Output Signals (Sheet 2 of 2)
Name
SBSY_C1#
SBSY_C2#
TDO
THRMTRIP#
THRMALERT#
Table A-13. Input Signals
Name
BPRI#
BR1#
BR2#
BR3#
BCLKp
BCLKn
D/C#
DEFER#
DHIT#
GSEQ#
ID[9:0]#
IDS#
INIT#
INT (LINT0)
IP[1:0]#
NMI (LINT1)
RESET#
RS[2:0]#
RSP#
PMI#
PWRGOOD
TCK
TDI
TMS
TRST#
TRDY#
NOTES:
1. Synchronous assertion with asserted RS[2:0]# guarantees synchronization.
106
Active Level Clock
Low BCLKp
Low BCLKp
High TCK
Low Asynchronous
Low Asynchronous
Active Level Clock
Low BCLKp
Low BCLKp
Low BCLKp
Low BCLKp
High —
High —
Low BCLKp
Low BCLKp
Low BCLKp
Low BCLKp
Low BCLKp
Low BCLKp
Low Asynch
High Asynch
Low BCLKp
High Asynch
Low BCLKp
Low BCLKp
Low BCLKp
Low Asynch
High Asynch
High —
High TCK
High TCK
Low Asynch
Low BCLKp
Signal Group
Data
Data
TAP
Error
Error
Signal Group
Arbitration
Arbitration
Arbitration
Arbitration
Control
Control
System Bus Request Phase (Mem Rd)
Snoop Snoop Phase
System Bus
Snoop Snoop Phase
Defer IDS#, IDS#+1
Defer
Exec Control
Exec Control
System Bus
Exec Control
Control
Response
Response
Exec Control
Control
Diagnostic
Diagnostic
Diagnostic
Diagnostic
Response Response Phase
Qualified
Always
Always
Always
Always
Always
Always
IDS#+1
Always
1
Always
IDS#+1
Always
Always
Always
—
Always
Always
Always
Always
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