Binit# (I/O); Bnr# (I/O); Bpm[5:0]# (I/O); Bpri# (I) - Intel Itanium 2 Processor Datasheet

Signals Reference
A.1.10

BINIT# (I/O)

If enabled by configuration, the Bus Initialization (BINIT#) signal is asserted to signal any bus
condition that prevents reliable future operation.
If BINIT# observation is enabled during power-on configuration, and BINIT# is sampled asserted,
all bus state machines are reset. All agents reset their rotating IDs for bus arbitration to the same
state as that after reset, and internal count information is lost. The L2 and L3 caches are not
affected.
If BINIT# observation is disabled during power-on configuration, BINIT# is ignored by all bus
agents with the exception of the priority agent. The priority agent must handle the error in a manner
that is appropriate to the system architecture.
BINIT# is a wired-OR signal.
A.1.11

BNR# (I/O)

The Block Next Request (BNR#) signal is used to assert a bus stall by any bus agent that is unable
to accept new bus transactions to avoid an internal transaction queue overflow. During a bus stall,
the current bus owner cannot issue any new transactions.
Since multiple agents might need to request a bus stall at the same time, BNR# is a wired-OR
signal. In order to avoid wired-OR glitches associated with simultaneous edge transitions driven by
multiple drivers, BNR# is asserted and sampled on specific clock edges.
A.1.12

BPM[5:0]# (I/O)

The BPM[5:0]# signals are system support signals used for inserting breakpoints and for
performance monitoring. They can be configured as outputs from the processor that indicate
programmable counters used for monitoring performance, or inputs from the processor to indicate
the status of breakpoints.
A.1.13

BPRI# (I)

The Bus Priority-agent Request (BPRI#) signal is used by the priority agent to arbitrate for
ownership of the system bus. Observing BPRI# asserted causes all other agents to stop issuing new
requests, unless such requests are part of an ongoing locked operation.The priority agent keeps
BPRI# asserted until all of its requests are completed, then releases the bus by deasserting BPRI#.
A.1.14

BR[0]# (I/O) and BR[3:1]# (I)

BR[3:0]# are the physical bus request pins that drive the BREQ[3:0]# signals in the system. The
BREQ[3:0]# signals are interconnected in a rotating manner to individual processor pins.
Table A-4
for both the 4P and 2P system bus topologies.
94
and Table A-4 give the rotating interconnection between the processor and bus signals
Datasheet