Analog Devices ADSP-21020 Specification Sheet page 16

ADSP-21020
Bus Request/Bus Grant
Parameter
Timing Requirement:
t BR Hold after CLKIN High
HBR
t BR Setup before CLKIN High
SBR
Switching Characteristic:
t Memory Interface Disable to BG Low –2
DMDBGL
t CLKIN High to Memory Interface
DME
Enable
t CLKIN High to BG Low
DBGL
t CLKIN High to BG High
DBGH
NOTES
*DT = t – 50 ns.
CK
Memory Interface = PMA23-0, PMD47-0, PMS1-0, PMRD, PMWR, PMPAGE, DMA31-0, DMD39-0, DMS3-0, DMRD, DMWR, DMPAGE.
Buses are not granted until completion of current memory access.
See the Memory Interface chapter of the ADSP-21020 User's Manual for BG, BR cycle relationships.
CLKIN
t
HBR
BR
MEMORY
INTERFACE
BG
K/B/T Grade K/B/T Grade B/T Grade
20 MHz
Min Max Min
0 0
18 15
–2
25 20
22
22
t
SBR
t
DBGL
Figure 8. Bus Request/Bus Grant
K Grade
25 MHz 30 MHz 33.3 MHz Frequency Dependency*
Max Min Max Min Max Min
0 0
13 12
–2 –2
16 15
22 22
22 22
t
HBR
t
DMDBGL
–16–
Max
18 + 5DT/16
25 + DT/2
22
22
t
SBR
t
DME
t
DBGH
Unit
ns
ns
ns
ns
ns
ns
REV. C