Analog Devices ADSP-21020 Specification Sheet page 25

Capacitive Loading
Output delays are based on standard capacitive loads: 100 pF
on address, select, page and strobe pins, and 50 pF on all others
(see Figure 14). For different loads, these timing parameters
should be derated. See the Hardware Configuration chapter of
the ADSP-21020 User's Manual for further information on
derating of timing specifications.
Figures 16 and 17 show how the output rise time varies with
capacitance. Figures 18 and 19 show how output delays vary
with capacitance. Note that the graphs may not be linear outside
the ranges shown.
10
9
8
7
6
5
4
3
1.46
2
1.31
1
0
25 50 75
LOAD CAPACITANCE – pF
NOTES:
(1) OUTPUT PINS BG, TIMEXP
(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0
Figure 16. Typical Output Rise Time vs. Load
Capacitance (at Maximum Case Temperature)
4
3
2
1.33
1
0.85
0
25 50 100
75
LOAD CAPACITANCE – pF
NOTES:
(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO
(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR
Figure 17. Typical Output Rise Time vs. Load
Capacitance (at Maximum Case Temperature)
REV. C
9.18
1
3.95
2
100 125 150 175 200
3.59
1
3.00
2
175 200
125 150
12
10
8
6
4
2
– 0.89
NOMINAL
–1.86
–2
25 50
NOTES:
(1) OUTPUT PINS BG, TIMEXP
(2) OUTPUT PINS PMD47–0, DMD39–0, FLAG3–0
Figure 18. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature)
3
2
1
NOMINAL
–1
– 1.70
–2
– 2.24
–3
25
50
NOTES:
(1) OUTPUT PINS PMA23–0, PMS1–0, PMPAGE, DMA31–0, DMS3–0, DMPAGE, TDO
(2) OUTPUT PINS PMRD, PMWR, DMRD, DMWR
Figure 19. Typical Output Delay or Hold vs. Load
Capacitance (at Maximum Case Temperature)
–25–
ADSP-21020
1
2
100 175
75 125 150
LOAD CAPACITANCE – pF
1
2
75 100 125 150 175
LOAD CAPACITANCE – pF
11.19
5.34
200
2.99
2.27
200