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ADSP-21020
TEST CONDITIONS
Output Disable Time
Output pins are considered to be disabled when they stop
driving, go into a high-impedance state, and start to decay from
their output high or low voltage. The time for the voltage on the
bus to decay by V is dependent on the capacitive load, C
the load current, I
. It can be approximated by the following
L
equation:
t
DECAY
The output disable time (t
DIS
t
and t
as shown in Figure 13. The time
MEASURED
DECAY
t
) is the interval from when the reference signal
MEASURED
switches to when the output voltage decays V from the
measured output high or output low voltage. t
calculated with V equal to 0.5 V, and test loads C
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high-impedance state to when they start
driving. The output enable time (t
a reference signal reaches a high or low voltage level to when the
output has reached a specified high or low trip point, as shown
in the Output Enable/Disable diagram. If multiple pins (such as
the data bus) are enabled, the measurement value is that of the
first pin to start driving.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
using the above equation. Choose V to be
DECAY
the difference between the ADSP-21020's output voltage and
the input threshold for the device requiring the hold time. A
typical V will be 0.4 V. C
is the total bus capacitance (per
L
data line), and I
is the total leakage or three-state current (per
L
data line). The hold time will be t
disable time (i.e. t
for the write cycle).
HDWD
REFERENCE
SIGNAL
V
OH (MEASURED)
OUTPUT
V
OL (MEASURED)
OUTPUT STOPS DRIVING
C
V
L
I
L
) is the difference between
is
DECAY
and I
L
) is the interval from when
ENA
plus the minimum
DECAY
t
MEASURED
t
DIS
V
OH (MEASURED)
V
OL (MEASURED)
t
DECAY
HIGH-IMPEDANCE STATE. TEST CONDITIONS
CAUSE THIS VOLTAGE LEVEL TO BE
APPROXIMATELY 1.5 V.
Figure 13. Output Enable/Disable
TO
OUTPUT
, and
L
PIN
* AC TIMING SPECIFICATIONS ARE CALCULATED FOR 100pF
DERATING ON THE FOLLOWING PINS: PMA23–0, PMS1–0, PMRD,
PMWR, PMPAGE, DMA31–0, DMS3–0, DMRD, DMWR, DMPAGE
Figure 14. Equivalent Device Loading For AC
Measurements (Includes All Fixtures)
.
L
INPUT OR
OUTPUT
Figure 15. Voltage Reference Levels For AC
Measurements (Except Output Enable/Disable)
t
ENA
2.0V
– V
+ V
1.0V
–24–
I
OL
*
50pF
I
OH
1.5V
V
OH (MEASURED)
V
OL (MEASURED)
OUTPUT STARTS DRIVING
+1.5V
1.5V
REV. C
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