Analog Devices ADSP-21020 Specification Sheet page 20

ADSP-21020
Memory Write
Parameter
Timing Requirement:
t xACK Delay from Address, Select
DAAK
t xACK Delay from xWR Low
DWAK
t xACK Setup before CLKIN High
SAK
t xACK Hold after CLKIN High
HAK
Switching Characteristic:
t Address, Select to xWR Deasserted
DAWH
t Address, Select to xWR Low
DAWL
t xWR Pulse Width
WW
t Data Setup before xWR High
DDWH
t Address, Select Hold after xWR
DWHA
Deasserted
t Data Hold after xWR Deasserted
HDWH
t xPAGE Delay from Address, Select
DAP
t CLKIN High to xWR Low
DCKWL
t xWR High to xWR or xRD Low
WWR
t Data Disable before xWR or xRD
DDWR
Low
t xWR Low to Data Enabled
WDE
NOTES
*DT = t – 50 ns
C
See "System Hold Time Calculation" in "Test Conditions" section for calculating hold times given capacitive and DC loads.
x = PM or DM; Address = PMA23-0, DMA31-0; Data = PMD47-0, DMD39-0; Select = PMS1-0, DMS3-0.
K/B/T Grade K/B/T Grade
20 MHz 25 MHz
Min Max Min Max
27 18
15 10
14 12
0 0
37 28
11 7
26 20
23 18
1 0
1
0 –1
1 1
16 26 13 24
17 13
13 9
0 –1
–20–
B/T Grade K Grade
30 MHz 33.3 MHz Frequency Dependency*
Min Max Min Max Min
12
6 9
10 5
0 9 14 + DT/4
0
21 18 37+ 15DT/16
5 3 11 + 3DT/8
16 15 26 + 9DT/16
14 13 23 + DT/2
0 0 1 + DT/16
–1 –1 DT/16
1 1
12 22 11 21 16 + DT/4 26 + DT/4
10 8 17 + 7DT/16
7 5 13 + 3DT/8
–1 –1 DT/16
Max Unit
27 + 7DT/8 ns
15 + DT/2 ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
REV. C