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Operation theory
Engine controller system
The engine gate array
The engine gate array is a supplementary device to the Engine CPU. The gate
array is a CMOS type, 4100-gate, 100-pin QFP that has the following internal
blocks.
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Pin assignment
Pin assignment for the engine gate array is table on the following pages. The device
in Remarks column means those which the signal is forwarded to.
Table 4. 3 g/a pin assignment—1/4
Pin no.
Signal
1
VSS
2
SYSCLK
OUT
3
TEST
IN
4
HEATON
OUT
5
FDON
OUT
6
FUON
OUT
7
REGPAP
IN
8
TCOVOP
IN
9
FCOVOP*
IN
10
SCOVOP*
IN
11
VSS
12
RSVIO1
IN/OUT
13
PAPER
IN
14
HANDS*
IN
15
TMOTON
OUT
FS-6750
Address decoder
Registers
Interrupt handler
Ports A to F
Data selector
Overrun detector
Port mode controller
Kyocera I/F controller
Print density controller
Laser power controller
Decoder g/a flash
High-voltage clock generator
Test-print controller
Engine CPU address-hold controller
Interlock controller
In/Out
Power terminal (Ground)
4 MHZ clock output
G/A test terminal
Fuser heater output, H: On
Face down switching output, H: Face down
selected
Face up switching output, H: Face up selected
Registration entry sensor paper detection input,
H: Paper detected
Top cover open/close detection input, H: Open
Feed unit open/close detection input, H: Open
Side cover open/close detection input, H: Open
Power terminal (Ground)
General-purpose input/output terminal 1
Cassette paper detection, H: Paper
MP tray paper detection, H: Paper
Toner motor on output, H: On
Function
4-27
Logic
Remarks
Engine CPU
Neg.
Neg.
Fuser unit
Neg.
Fuser unit
Reg. sensor
Top cover
Feed cover
Side cover
Fixed low
Cassette
MP tray unit
Neg.
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