Kyocera Mita FS-6750 Service Manual page 87

Operation theory
Engine controller system
Table 4. 3 g/a pin assignment—3/4
Pin no. Signal
59 SCLKOUT OUT
60 VDD
61 VSS
62 SOOUT OUT
63 SBSY* OUT
64 VDFON1* OUT
65 EGIR OUT
66 STRIG OUT
67 SDIR OUT
68 SCLKIN IN
69 SOIN IN
70 FRCS* OUT
71 VSS
72 TEST2 OUT
73 GAINT OUT
74 WR* IN
75 RD* IN
76 VDD
77 ALE IN
78 RESET* IN
79 DBRX IN
80 DBCLK IN
81 VSS
82 DBTX OUT
83 LA7 OUT
84 LA6 OUT
85 LA5 OUT
86 LA4 OUT
87 LA3 OUT
88 LA2 OUT
89 LA1 OUT
90 LA0 OUT
91 VSS
92 A19 IN
93 A18 IN
94 A17 IN
95 AD7 IN/OUT
96 AD6 IN/OUT
97 AD5 IN/OUT
98 AD4 IN/OUT
99 AD3 IN/OUT
100 AD2 IN/OUT
101 VSS
102 AD1 IN/OUT
103 AD0 IN/OUT
104 FANON* OUT
FS-6750
In/Out
Main I/F serial clock output
Power terminal
Power terminal (Ground)
Main I/F serial data output
Main I/F status busy output, L: Busy
Forced light emission period notification signal 1,
L: Forced light emission period
Main I/F engine interrupt output, H: Interrupt
Not used
Main I/F status/command discrimination output
Main I/F serial clock input
Main I/F serial data input
Flash ROM chip select output, L: Enable
Power terminal (Ground)
Output terminal for engine debugging
Engine interrupt output, H: Interrupt
Bus right signal input
Bus read signal input
Power terminal
Address latch input
Reset input, L: Reset period
Engine debugger serial data input
Engine debugger serial clock input
Power terminal (Ground)
Engine debugger serial data output
Latch address
Latch address
Latch address
Latch address
Latch address
Latch address
Latch address
Latch address
Power terminal (Ground)
Engine CPU address
Engine CPU address
Engine CPU address
Engine CPU address/data bus
Engine CPU address/data bus
Engine CPU address/data bus
Engine CPU address/data bus
Engine CPU address/data bus
Engine CPU address/data bus
Power terminal (Ground)
Engine CPU address/data bus
Engine CPU address/data bus
Printer fan on output, L: On
Function
4-29
Logic Remarks
Main I/F
Main I/F
Main I/F
Pos. Main I/F
Main I/F
Main I/F
Main I/F
Main I/F
Pos. Flash ROM
Neg.
Engine CPU
Neg.