Figure 3-2 Internal Ramdac Block Diagram - Rastergraf Eclipse3 Series User Manual

Rastergraf
3.2.10 Internal RAMDAC and PLL Clock Generators
The RAMDAC transforms the raw data from the CRT controller into
signals that an analog or digital monitor can understand. In the process, it
can add gamma correction and a high resolution cursor. The RAMDAC
also provides two programmable clocks which can range from 25 MHz to
250 MHz: one for the memory controller, and the other for the pixel data.
Feature Summary
• 250 MHz operation
• 128-bit > 64-bit multiplexer from the pixel FIFO
• Fine-grained PLL programming optimizes display
• Pixel re-synchronization ensures integrity of all display modes
• Large Screen ISO-compliant refresh rates
• 8/15/16/32-bits per pixel
• 32 bpp Direct Color Gamma correction
• 256-shade gray scale
• Three 256x8 color palette RAMs
• Triple monotonic 8-bit DACs
• 64x64/32x32 translucent hardware cursor
• 100 MHz 8-bit VGA data input
• On-chip diagnostic functions
• Power-down modes

Figure 3-2 Internal RAMDAC Block Diagram

Programming On-board Devices 3-7