Borealis Graphics Accelerator; Host Bus Interface; Frame Buffer - Rastergraf Eclipse3 Series User Manual

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3.2 Borealis Graphics Accelerator

Note
The Borealis Technical Manual is available from Rastergraf under NDA.
3.2.1 Introduction
This section describes the architecture and includes a block diagram for
Borealis high performance graphics controller, which includes a 33/66
MHz PCI compliant interface with no additional external logic required.
Please see the following page for a Block Diagram of the Borealis.
Software may interact with Borealis by directly manipulating pixels
through the frame buffer interface or by the Borealis3D's highly pipelined
graphic processor architecture. This architecture allows for high
performance 2D and 3D Rendering. After a sequence of commands and
parameters are written, Borealis executes the selected command without
any further host processor intervention.

3.2.2 Host Bus Interface

The Host Bus Interface provides an interface to the PCI system bus. It
implements a full PCI slave interface, responding to reads and writes of
configuration, memory, and I/O cycles. It also implements a PCI master
interface for specific memory writes. It also generates peripheral bus
control for flash EPROM.

3.2.3 Frame Buffer

Borealis supports one local frame buffer of up to 32 MB with a data bus
width of 128 bits to SGRAM memory. The local buffer may be used as a
display buffer, as well as off-screen memory to be used for the storage and
manipulation of bitmaps, texture maps, Z buffering or fonts. The buffer
may be accessed as a linear buffer through the Frame Buffer interface or
through the drawing engine.
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Programming On-board Devices 3-3