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Rastergraf Eclipse3 Series User Manual

Graphics boards for pmc, pci and compactpci
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Eclipse3 Series
User's Manual
Graphics Boards for PMC, PCI and CompactPCI
Compatible Computers
Rastergraf
Rastergraf, Inc.
1804-P SE First St.
Redmond, OR 97756
(541) 923-5530
FAX (541) 923-6475
web:
http://www.rastergraf.com
Release 2.0
March 5, 2008

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  • Page 1 Eclipse3 Series User’s Manual Graphics Boards for PMC, PCI and CompactPCI Compatible Computers Rastergraf Rastergraf, Inc. 1804-P SE First St. Redmond, OR 97756 (541) 923-5530 FAX (541) 923-6475 web: http://www.rastergraf.com Release 2.0 March 5, 2008...

  • Page 2: Table Of Contents

    Table of Contents INTRODUCTION..................Introduction-1 .........................Introduction-2 ETTING ........................Introduction-2 OARD EVISIONS ...........................Introduction-3 OTICES ..................Introduction-4 ONVENTIONS ANUAL CHAPTER 1 GENERAL INFORMATION .............. 1-1 1.1 I ........................... 1-1 NTRODUCTION 1.2 F ......................... 1-2 UNCTIONAL ESCRIPTION 1.3 A ........................1-6 DDITIONAL EFERENCES 1.3 A ........................
  • Page 3 Table 1-2 Eclipse3 FCode/Solaris Platform Display Timing Specifications....1-10 Table 1-3 Eclipse3 VGA/Windows Platform Display Timing Specifications ..... 1-10 Table 1-3 Rastergraf Ruggedization Levels Chart............1-13 Table 1-4 Analog (VGA) Video Connector Pinout ............1-16 Table 1-5 DVI-I Connector Pinout ................1-17 Table 1-6 Eclipse3 Software..................

  • Page 5: Introduction

    Introduction This manual provides information about how to configure, install, and program the Rastergraf Eclipse3 128-bit graphics display controllers. Software support is available for Solaris, Linux, VxWorks, LynxOS, and Windows 2000 and XP. They are available for PMC PCI, and CompactPCI compatible computers.

  • Page 6: Getting Help

    2) fax your questions to (541) 923-6475 3) send E-mail to support@rastergraf.com. If your problem is monitor related, Rastergraf technical support will need detailed information about your monitor. Board Revisions This manual applies to the following board revision levels: Eclipse3PMC Fab Rev 1.2A...

  • Page 7: Notices

    Rastergraf assumes no responsibility for the use or reliability of software or hardware that is not supplied by Rastergraf, or which has not been installed in accordance with this manual. The Eclipse3 graphics boards are manufactured and sold under license from Curtiss-Wright Controls Embedded Computing (CWCEC).

  • Page 8: Conventions Used In This Manual

    Rastergraf Conventions Used In This Manual The following list summarizes the conventions used throughout this manual. Code Code fragments, file, directory or path names and fragments user/computer dialogs in the manual are presented in the courier typeface. Commands or Commands, or the names of executable programs, program names except those in code fragments, are in bold.

  • Page 9: Chapter 1 General Information

    Chapter 1 General Information 1.1 Introduction The Rastergraf Eclipse3 is part of Rastergraf ’s broad line of graphics modules for use in PMC, PCI, VME, and CompactPCI computers. For information about all of Rastergraf ’s products, please contact Rastergraf Worldwide Sales at (541) 923-5530 or consult Rastergraf ’s web page at http://www.rastergraf.com.

  • Page 10: Functional Description

    1.2 Functional Description As an aid to understanding the Eclipse3, a block diagram is provided at the end of this section. The feature set includes: • 128-bit Rastergraf Borealis 2D/3D Graphics Controller • 33/66 MHz 32-bit PCI bus • Embedded VGA controller •...
  • Page 11 Rastergraf 1.2.1 Borealis Graphics Controller The Rastergraf Borealis 2D/3D graphics controller chip is a 128-bit graphics controller with accelerated 2D and 3D patterned lines and shaded triangles, Z buffer, and 3D volume clipping. It provides a high performance 33/66 MHz PCI 2.1 compliant interface with no additional external logic required.

  • Page 12: Figure 1-1 Borealis Block Diagram

    Rastergraf The Borealis design is based on technology licensed by Rastergraf from S3/Number Nine. The chip itself is manufactured for Rastergraf by LSI Logic using LSI’s .35u G-10P ASIC process. The Borealis graphics controller is implemented using a highly pipelined graphic processor architecture.

  • Page 13: Figure 1-2 Dvi Digital Video Block Digram

    Connections to the Eclipse3 are made through the front DVI-I connector. Figure 1-2 DVI Digital Video Block Digram 1.2.3 Software Support Rastergraf software support is available for many operating systems. Support for multiple display heads is included. The software packages are: SDL Graphics Subroutine Library Windows 2000/XP Drivers Sun/Solaris Accelerated 2D and 3D DDX X Window System Server Complete X Windows X11R6 server based on Xfree86 Version 4.2...
  • Page 14 Rastergraf 1-6 General Information...

  • Page 15: Additional References

    Rastergraf 1.3 Additional References You can find Rastergraf documentation and technical literature on the Rastergraf web page (http://www.rastergraf.com). The CompactPCI Specification – PICMG R2.0 R3.0, the CompactPCI Hot Swap Specification – PICMG 2.1 R2.0 and the CompactPCI Hot Swap Infrastructure Interface Specification PICMG 2.12 R1.0 standards...

  • Page 16: Specifications For The Eclipse3

    8-bit pixels, four pages using 16-bit pixels, or two pages using 32 bpp. 24 bpp packed pixel mode is not supported. EEPROM Memory: 128 KB Flash EEPROM contains the Rastergraf Quad Image BIOS (QIB) that supports SPARC FCode, VGA BIOS, DVI, and Sync-On-Green (SOG). A user jumper enables the QIB to select SOG.
  • Page 17 The standard front panel analog VGA connector is replaced by a DVI-I connector. This connector supplies both the digital DVI (TMDS) signals and VGA. Rastergraf can supply an adapter that allows a standard VGA cable to be used when a DVI display is not desired or available.
  • Page 18 Rastergraf Table 1-2 Eclipse3 FCode/Solaris Platform Display Timing Specifications Active Analog/ Bits per Vertical Horizontal Pixel Display Index Pixel Refresh Refresh Clock 60 Hz 31.5 KHz 25.2 MHz 640 x 480 Both 8, 16, 32 75 Hz 37.5 KHz 31.5 MHz 60 Hz 37.9 KHz...
  • Page 19 Rastergraf Fuse Element: The +5V supplied to the front panel connectors is protected by a Positive Temperature Coefficient (PTC) resistor. It resets automatically when the overload is removed. Local I C Channel: The Eclipse3 uses I C, a 2 wire serial bus, to control the...
  • Page 20 An LM75 thermal sensor provides limit flags and real-time temperature read-back. Ruggedization Option: Rastergraf offers semi-ruggedized versions of the Eclipse3 boards include a MIL-compliant silicone or acrylic conformal coating and extended temperature testing. Rastergraf board designs use standard distribution commercial temperature range parts.
  • Page 21 At the time of writing, complete shock and vibration testing has not been performed, but some boards have been tested enough to expect full acceptance is possible. Please contact Rastergraf Sales if you need this information. Table 1-3 Rastergraf Ruggedization Levels Chart Conduction-...

  • Page 22: Eclipse3 Connectors And Cables

    DDC/DDA monitor control signals, as well as DVI digital video output. An adapter connector (Molex 88741-8700, available from Digikey) is available from Rastergraf that adapts the DVI-I to a standard VGA connector. The CPCI rear-panel I/O option includes a rear I/O module with VGA and/or DVI connectors mounted to either a 3U or 6U panel.

  • Page 23: Vga Connector

    (75 ohms) to standard RS-330/IRE levels. Cable length should be limited to 50 feet unless you use low loss RG-59. Rastergraf has used an outside cable shop to build production cables: Lynn Products, Inc. http://www.lynnprod.com If you really want to roll you own, the PMC board side connector is an AMP 177802-3.
  • Page 24 Rastergraf Table 1-4 Analog (VGA) Video Connector Pinout Description Ground Type Cable Type 75 ohm Coax with pin 6 Green 75 ohm Coax with pin 7 Blue 75 ohm Coax with pin 8 not used DDC Ground Circuit Ground Red Ground...
  • Page 25 Rastergraf strongly urges you to obtain commercially manufactured cables and/or adapters that are available from Rastergraf, Molex, and other suppliers. But, if you really want to roll you own, the board side connector part number is Molex 74320-1004 with Molex 71781-0001 (or equivalent) jackposts with Loctite.
  • Page 26 Rastergraf 1.5.3 Connections to the PMC Bus PINTAL BUSMODE1L VCC (5V) BUSMODE2L VDD (3.3V) PCICLK PCIRSTL BUSMODE3L PMCGNTL VDD (3.3V) BUSMODE4L 16 PMCREQL VCC (5V) byp (Vio) AD31H AD30H AD29H AD28H AD27H AD26H AD25H AD24H VDD (3.3V) C/BE3L IDSEL AD23H...
  • Page 27 Rastergraf 1.5.4 Connections to the PCI Bus SIDE A SIDE B SIDE A SIDE B VDD (3.3V) PCBE2L PFRAMEL PIRDYL JTAGTDIOH JTAGTDIOH PTRDYL VDD (3.3V) VCC (5V) VCC (5V) PDEVSELL PINTAL VCC (5V) PSTOPL VDD (3.3V) VCC (5V) PRSNT1L VDD (3.3V)
  • Page 28 Rastergraf 1.5.4 Connections to the PCI Bus (continued) SIDE A SIDE B byp (Vio) byp (Vio) byp (Vio) byp (Vio) byp (Vio) byp (Vio) Note: byp means the pin is connected to a bypass capacitor on the graphics board but is...
  • Page 29 Rastergraf 1.5.5 J1 Connections to the CompactPCI Bus byp (+12V) VCC (5V) byp (-12V) (5V) VCC (5V) TDIOH TDIOH INTA# VCC (5V) byp (Vio) PCIRSTL GNT# PCIREQ# VDD (3.3V) PCICLK AD[31] AD[30] AD[29] AD[28] AD[27] AD[26] byp (Vio) AD[25] AD[24]...
  • Page 30 Note: byp means the pin is connected to a bypass capacitor on the graphics board but is otherwise not used Pins used for Rear Panel I/O are used in Slot 1. This board MUST NOT be installed in Slot 1. PK_GND are grounds that are added by Rastergraf. 1-22 General Information...

  • Page 31: Monitor Requirements

    Rastergraf 1.6 Monitor Requirements Rastergraf graphics boards can be used with a variety of monitors. For best performance a monitor should have the following features: • VGA compatible 5 Wire RGB with separate TTL horizontal and vertical sync or 3 Wire RGB with sync on green (see note below) •...

  • Page 32: Configuration Information

    Rastergraf 1.7 Configuration Information The basic graphics board includes: • Rastergraf Borealis Graphics Processor with 8, 16, or 32 bit/pixel • 16 MB SGRAM • hardware interrupts, pan, scroll, and zoom and cursors • analog video outputs • Quad Image BIOS supports VGA, FCode, DVI, and Sync on Green (SOG) An on-board 3.3V regulator can be provided on the PMC and PCI boards...

  • Page 33: Chapter 2 Installing Your Peritek Graphics Board

    Chapter 2 Installing Your Peritek Graphics Board 2.1 Introduction There are 2 steps involved in getting your Rastergraf Graphics board to work in your system: • Unpack and install the Rastergraf graphics board. • Install the software This chapter shows you how to install the Rastergraf graphics board in your computer.

  • Page 34: Unpacking Your Board

    When you unpack your board, inspect the contents to see if any damage occurred in shipping. If there has been physical damage, file a claim with the carrier at once and contact Rastergraf for information regarding repair or replacement. Do not attempt to use damaged equipment.

  • Page 35: Preparing For Installation

    RAMDAC, DDC2B/ I C control lines, and SGRAM. The Rastergraf Eclipse3 device driver will load the BARs if the O/S or BIOS did not. If you can determine the actual PCI base address, you might even be able to probe the address spaces with an on-line debugger once the driver code has run.
  • Page 36 BIOS from loading the Eclipse3 BIOS code twice. JP101: Sync-On-Green Select Jumper The Eclipse3 has the Rastergraf Quad Image BIOS (QIB) PROM, which supports FCode, VGA, DVI, and Sync-On-Green (SOG). The firmware can “determine” the need to run FCode or VGA and if the DVI monitor is plugged in, it will select DVI mode without user intervention.

  • Page 37: Eclipse3Pmc Graphics Board Installation

    Older VME host or carrier boards may not supply 3.3V to the PMC connectors and the Eclipse3 PMC boards require both 3.3V and 5V. By special order, Rastergraf can supply the graphics board with a local 3.3V regulator installed. Please contact Rastergraf for assistance.

  • Page 38: Figure 2-1 Jumper Locations For The Fab Rev 1.2 Eclipse3Pmc Board

    Rastergraf Figure 2-1 Jumper Locations for the Fab Rev 1.2 Eclipse3PMC Board JP202 - Reserved JP201 VGA Sub-class Device Enable JP203 Fab Revision Optional Local Number 3.3V Power JP101 Sync-On-Green Jumper 2-6 Installing Your Peritek Graphics Board...

  • Page 39: Figure 2-2 Installation Of A Pmc Module Into An Emerson Mvme2604

    Rastergraf 2. Open the computer and remove the CPU board onto which the graphics PMC board is to be installed. Identify an empty PMC location (generally there are one or two on a given CPU board). The graphics PMC board is a Universal PMC/PCI device and can be plugged into a PMC port which uses either 5V or 3.3V signaling.

  • Page 40: Figure 2-3 Installation Of A Pmc Module Into The Pmb-C

    Rastergraf Figure 2-3 Installation of a PMC Module into the PMB-C l o t l o t 2-8 Installing Your Peritek Graphics Board...

  • Page 41: Figure 2-4 Installation Of The Pmc Module Into An Emerson Cpv3060

    Rastergraf Figure 2-4 Installation of the PMC Module into an Emerson CPV3060 4. Touch a metal part of the computer chassis, remove the graphics board from its anti static bag, and immediately slip it into the slot. After ensuring that the board is seated correctly, install the mounting screws (two near the front and two near the PMC connectors).

  • Page 42: Eclipse3Pci Board Installation

    3.3V to the PCI connectors. If the computer is listed as PCI 2.0 or 2.1 compliant, it probably does not supply 3.3V. By special order, Rastergraf can supply the graphics board with a local 3.3V regulator installed. Please contact Rastergraf for assistance.

  • Page 43: Figure 2-5 Jumper Locations For The Eclipse3Pci Board

    Rastergraf Figure 2-5 Jumper Locations for the Eclipse3PCI Board 32/64 bit PCI slot JP201 JP101 Flash Bank Fab Revision Number JP233 Local 3.3 Installing Your Peritek Graphics Board 2-11...

  • Page 44: Figure 2-6 Installation Of A Pci Module Into An Emerson Mtx

    Rastergraf Caution The static electricity that your body builds up normally can seriously damage the components on the graphics board. 3. Wear a grounded wrist strap and touch a metal part of the computer chassis. Remove the card slot blocking plate from the chassis. Then, remove the graphics board from its anti static bag, and immediately slide it into the slot.

  • Page 45: Eclipse3Cpci Board Installation

    Rastergraf 2.6 Eclipse3CPCI Board Installation The Eclipse3CPCI board can plug into any 32-bit, 5V or 3.3V signaling CompactPCI 3U or 6U slot. Although the board is usually supplied with a 6U faceplate, a 3U faceplate is also available. The board uses only the J1 connector unless the Rear I/O option is included.

  • Page 46: Figure 2-7 Jumper Locations For The Eclipse3Cpci Board

    Rastergraf Figure 2-7 Jumper Locations for the Eclipse3CPCI Board JP201 Fab Revision Number JP101 Flash Bank JP102 Frame/Chassis Ground 2-14 Installing Your Peritek Graphics Board...

  • Page 47: Figure 2-8 Installing A Compactpci Board

    Rastergraf Caution The static electricity that your body builds up normally can seriously damage the components on the graphics board. 4. Wear a grounded wrist strap. Touch a metal part of the computer chassis, remove the graphics board from its anti static bag, and immediately slide it into the slot.

  • Page 48: Finishing The Installation

    If you have an Eclipse3 Standard version board, plug a VGA cable into the VGA compatible front panel connector. If you have an DVI option board, use either a Rastergraf supplied breakout cable or your own cable solution and plug into the DVI-I connector on the graphics board’s front panel.

  • Page 49: Using An Eclipse 3 Board In Apc

    86 4.2 support multihead operation. Single Graphics Board If you are using a PC and the Rastergraf board is to be the system display (and you don't have another VGA controller installed), the system BIOS should find the Rastergraf board, and initialize the display.
  • Page 50 BIOS. This screen will identify the Borealis board BIOS, the revision and build date, and copyright Rastergraf Corp. Additional messages will be displayed if a DVI option is found, if a DVI monitor is connected, if it is a Sync-On- Green...
  • Page 51 Rastergraf Table 2-1 x86 Supported Video Modes Type Code Text Graphics Color Range PC Mode 0x00,1 40x25 4 bits per pixel 0x02,3 80x25 2 bits per pixel 0x04,5 40x25 320x200 4 bits per pixel 0x06 80x25 640x200 monochrome 0x07 80x25...

  • Page 52: Using An Eclipse 3 Board In Asparc Cpu

    OpenBoot to correctly identify the graphics board on startup and use it as the console. Single Graphics Board If the Rastergraf board is to be the system display (and you don't have another display board installed), OpenBoot should find the Rastergraf board, and initialize the display.
  • Page 53 2.9.2.2 NVEDIT Command Summary The next section makes use of the OpenBoot nvedit utility to change the default settings for the Rastergraf FCode that are maintained in the nvramrc file by OpenBoot. NVEDIT Commands Go to the next line...
  • Page 54 Rastergraf 2.9.2.3 Setting the Console Resolution The initial system default console resolution of the Eclipse3 is 8 bits per pixel, 1152 x 864 @ 60Hz. The Eclipse3 is capable of supporting additional console mode resolutions (all are 8 bpp) as shown in the...
  • Page 55 Rastergraf 2.9.2.4 Setting the Sync Mode The initial system default sync signal output type of Eclipse3 is separate, positive polarity. Eclipse3 is capable of generating additional sync output signals as shown in the following table: Table 2-3 FCode Sync Output Modes...
  • Page 56 Rastergraf 2.9.2.5 Setting the Console Background and Text Display Appearance The initial system default console background and text display appearance is Black Text on a White Background.. Alternatively, White Text on a Black Background (it will look like this: To change the appearance, enter the new mode (0 for Black Text, 1 for in place of the word , as shown below.

  • Page 57: Using An Eclipse3 Board In A Powerpc

    If you have any trouble with any part of the installation call or email Rastergraf for assistance, or refer to Chapter 4. Installing Your Peritek Graphics Board 2-25...

  • Page 59: Chapter 3 Programming On-Board Devices

    Rastergraf offers a variety of software to support the Eclipse3 graphics boards in Solaris, Windows 2000, and XP, VxWorks, and Linux. These offerings are covered in detail on the Rastergraf web page.
  • Page 60 SDL device support cover that pretty well. The sections summarize the devices and include some “hints and kinks”. You can refer to the Rastergraf web site for complete documentation. You can also license the Rastergraf SDL source code itself.

  • Page 61: Borealis Graphics Accelerator

    Rastergraf 3.2 Borealis Graphics Accelerator Note The Borealis Technical Manual is available from Rastergraf under NDA. 3.2.1 Introduction This section describes the architecture and includes a block diagram for Borealis high performance graphics controller, which includes a 33/66 MHz PCI compliant interface with no additional external logic required.

  • Page 62: Figure 3-1 Borealis Block Diagram

    Rastergraf Block Diagram Borealis is partitioned into the following functional sections: • Host Bus Interface • Aperture Controller • Drawing Engine • CRT Controller • Memory Controller • Internal VGA • Internal RAMDAC CS[0,2] DQM[15:0] Linear ADR[11:0] Windows Controller Memory...

  • Page 63: Linear Windows Controller

    Rastergraf 3.2.4 Linear Windows Controller The Linear Windows Controller provides address decoding, address translation, color space conversion between the host interface and the local memory system. It also provides a mechanism for caching reads and writes from the host bus to the local buffers. In write mode, up to eight 32 bit words may be written to the host bus cache.

  • Page 64: Memory Controller

    Rastergraf 3.2.6 Display List Processor The Display List Processor (DLP) is used to feed a set of commands to the Drawing Engine. The DLP uses a 128-bit instruction word. The instruction formats allow for each word to write up to three Drawing Engine registers or two text glyphs.

  • Page 65: Figure 3-2 Internal Ramdac Block Diagram

    Rastergraf 3.2.10 Internal RAMDAC and PLL Clock Generators The RAMDAC transforms the raw data from the CRT controller into signals that an analog or digital monitor can understand. In the process, it can add gamma correction and a high resolution cursor. The RAMDAC also provides two programmable clocks which can range from 25 MHz to 250 MHz: one for the memory controller, and the other for the pixel data.
  • Page 66 Rastergraf 3.2.11 Coordinate System The screen coordinate system has its origin at the upper left hand corner of the screen, with the X coordinates incrementing left to right and the Y coordinates incrementing top to bottom. The coordinate system for a 1280 by 1024 display is shown in below.
  • Page 67 0 ohm resistors installed during manufacturing and read by the Borealis on power up. Note: Software cannot override the values set by the 0 ohm resistors. Please contact Rastergraf if it is necessary to change a value. Table 3-1 Borealis Configuration Settings In/Out...

  • Page 68: Borealis Clocks

    Rastergraf 3.3 Borealis Clocks The Eclipse3 boards have several clocks. DECLK is the Borealis Drawing Engine clock and is generated by the CY2292 clock synthesizer. A two frequency select allows the DECLK to be set to 75, 80, 90, or 100 MHz, depending on the operating conditions of the system.

  • Page 69: Synchronous Graphics Ram (Sgram)

    Rastergraf 3.4 Synchronous Graphics RAM (SGRAM) The display memory chips are expressly designed for high speed graphics applications. These devices are called Synchronous Graphics RAMs (SGRAMs). The SGRAM replaces the previously used Video RAM, which had a two- port design with separate video output that drove an external RAMDAC.

  • Page 70: Eclipse3 Optional Features Register

    Rastergraf Display Memory Size The pixel size is programmable to 8, 15, 16, or 32 bpp. The SGRAM on the Borealis is either 16 MB or 32 MB, where a MB = 1024 * 1024 bytes. Calculate the possible display formats based on these values.

  • Page 71: Video Timing Parameters

    3.6 Video Timing Parameters The Borealis must be programmed to generate the proper video timing for the hardware configuration and display format. Rastergraf ’s SDL subroutine library package accepts display format (e.g. 1600 x 1200, 32 bpp) and refresh requirements (e.g. 67 Hz vertical refresh) as parameters to a function call.
  • Page 72 Vertical Size. It is recommended that the monitor adjustments be tried before trying monitor settings not in accord with the monitor data sheet. Rastergraf ’s SDL software allows you to define the timing parameters in one of two ways: a) you tell SDL that you are using a multiscan monitor. You specify the display active width and height (e.g.

  • Page 73: Figure 3-3 Video Display Timing Fields

    Rastergraf Figure 3-3 Video Display Timing Fields Horizontal Total Horizontal Blanking End Horizontal Retrace End Horizontal Retrace Start Horizontal Blanking Start Horizontal Display End Active Display Area Vertical Border Vertical Blank Vertical Retrace Vertical Blank Vertical Border To change the horizontal frequency: The horizontal frequency is also known as horizontal refresh or scan rate.
  • Page 74 Rastergraf To change the vertical frequency: The vertical frequency is also known as vertical refresh rate or vertical scan rate. Indications that the vertical frequency needs to be changed are a picture which rolls up or down. Sometimes the appearance is of multiple pictures, one on top of another, with multiple horizontal lines.
  • Page 75 3.6.3 Request for Help in Determining Video Timing Values Use the following table to request help when you have a non-standard video timing requirement. Table 3-4 Eclipse3 Video Timing Parameter Request Form Submit to: Rastergraf Technical Support Fax (541) 923-6475 or email: support@rastergraf.com Company Information Company Name_______________________________...

  • Page 76: System Management Devices And Functions

    Memory Clock PLL allow the system to optimize operating frequencies for the Borealis as a function of system temperature. Please contact Rastergraf for more information if you wish to utilize any or all of these features. 3-18 Programming On-board Devices...
  • Page 77 Rastergraf 3.8 Talk To Me Through I The Borealis chip has a control register that is used to implement the I protocol, a 2 wire serial bus designed Philips Semiconductor. The Borealis is the I C master and it controls the bus through the DDC control register in the Borealis chip.

  • Page 78: Dvi Digital Video Output

    The THC63DV164 is programmed though an I slave interface. It supports Receiver and Hot Plug Detection for a variety of power management options. You can obtain the data sheet for the THC63DV164 from the technical document section on the Rastergraf web site Features •...

  • Page 79: Figure 3-5 Thc63Dv164 Rgb To 24-Bit Tmds Mapping Diagram

    Rastergraf Figure 3-5 THC63DV164 RGB to 24-bit TMDS Mapping Diagram 24-bit Input Mode (BSEL = 1) D[23:0] IDCK+ DSEL = 0, EDGE = 0 IDCK+ DSEL = 0, EDGE = 1 IDCK+ DSEL = 1 First Latching Edge 24-bit Mode Data Mapping...

  • Page 80: Flash Eeprom

    Programmable Read Only Memory (EEPROM). The programming of the Serial EEPROM is done through control lines on the Borealis chip. Rastergraf reserves the first 128 bytes of the 256 byte Serial EEPROM for internal use. The remaining 128 bytes are left for user data. The use of the serial EEPROM on the Eclipse3 does not currently have formal Rastergraf software support.

  • Page 81: Chapter 4 Troubleshooting

    Rastergraf Chapter 4 Troubleshooting Introduction This chapter contains information which should assist you in tracking down installation and functional problems with your board. 4.1 General procedures 4.2 Dealing with the PCI bus 4.3 Maintenance, Warranty, and Service...

  • Page 82: General Procedures

    You may be able to locate minor problems without technical assistance. If the problem can not be remedied, Rastergraf can then issue a Return Material Authorization (RMA) so that the board can be returned to the factory for quick repair.

  • Page 83: Dealing With The Pci Bus

    CPU boards, even when they use the same CPU and PCI bridge. Therefore, if you plan to use an Eclipse3 graphics board in a PowerPC based system, it is vital to ensure that Rastergraf can vouch for the board’s operation before you order the board. Otherwise, you may go crazy trying to figure out why it doesn’t work.

  • Page 84: Return Policy

    If extensive repairs are required, Rastergraf will request authorization for an estimated time and materials charge. If replacement is required, additional authorization will be requested. All repair work will be done at the Rastergraf factory in Redmond, Oregon, unless otherwise designated by Rastergraf. 4-4 Troubleshooting...
  • Page 85 Rastergraf Index 5 wire VGA monitors, 2-16 LM75, 1-11, 1-12, 3-18, 3-19 ACE Series, 0-1, 1-1, 1-2, 1-5, 1-8, 1-9, 1- Maintenance, 4-3 10, 1-14, 1-23, 1-24, 2-3, 2-4, 2-5, 2-6, 2- Memory controller 10, 2-11, 2-13, 2-14, 2-16, 2-17, 2-20, 3-1,...

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