Rastergraf Eclipse3 Series User Manual page 30

Rastergraf
1.5.5 J2 Connections to the CompactPCI Bus (optional)
Z A
1 GND PK_GND
2 GND RIO_TX2L
3 GND RIO_TX2H
4 GND VIO
5 GND
6 GND
7 GND
8 GND
9 GND
10 GND
11 GND
12 GND
13 GND
14 GND
15 GND
16 GND
17 GND
18 GND
19 GND GND
20 GND RIO_TXCH
21 GND RIO_TXCL
22 GND n/c
Note: byp means the pin is connected to a bypass capacitor on the
1-22 General Information
B
GND RIO_BVSYNC
VCC
GND RIO_BHSYNC
GND
GND
GND
GND
GND
GND
GND
GND
GND
n/c
graphics board but is otherwise not used
Pins used for Rear Panel I/O are used in Slot 1. This board MUST
NOT be installed in Slot 1.
PK_GND are grounds that are added by Rastergraf.
C D
RIO_DDCH
RIO_TX1L
RIO_TX1H
GND
VIO
GND
VIO
GND
VIO
GND
VIO
GND
VIO
GND
RIO_BLU
GND
RIO_GRN
GND
GND
n/c n/c
E F
PK_GND GND
RIO_TX0L GND
RIO_TX0H GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
RIO_RED GND
GND
RIO_DDAH GND
GND
GND
GND
GND
n/c GND