Figure 1-1 Borealis Block Diagram - Rastergraf Eclipse3 Series User Manual

Rastergraf
The Borealis design is based on technology licensed by Rastergraf from
S3/Number Nine. The chip itself is manufactured for Rastergraf by LSI
Logic using LSI's .35u G-10P ASIC process.
The Borealis graphics controller is implemented using a highly pipelined
graphic processor architecture. This architecture allows for high
performance 2D and 3D rendering. After a sequence of commands and
parameters are written, the Borealis executes the selected command
without any further host processor intervention. A Display List Processor
enables the Borealis to repetitively execute strings of commands.
The Borealis supports a local frame buffer with up to 32 MB SGRAM
using a 128-bit wide data bus. The frame buffer may be accessed as linear
buffers through the frame buffer interface or through the drawing engine.
The large local buffer may be used as a display buffer, as well as off-
screen memory to be used for the storage and manipulation of bitmaps,
texture maps, Z buffering or fonts.
1-4 General Information

Figure 1-1 Borealis Block Diagram

AD[31:0]
BE[3:0]
Host Bus
Interface
CNTRL[6:0]
HBCLK
RST
Linear
Windows
Controller
Memory
Display
List Controller
Processor
2D/3D
Drawing
Engine
VGA
Internal
CRT
RAMDAC
Controller
CS[0,2]
DQM[15:0]
ADR[11:0]
WE
RAS
CAS
SF
PA[7:0]
PD[7:0]
CJ[15:0]
MCLK
PXD[127:0]
HSYNC
VSYNC
BLANK
RED
GREEN
BLUE
CRTclk
DDC, DDA