Intel Quickpath Interconnect - Intel S2600CO series User Manual

Functional Architecture Overview
Processor Core Features:
Up to twelve execution cores
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Each core supports two threads (Intel
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per socket
46-bit physical addressing and 48-bit virtual addressing
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1 GB large page support for server applications
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A 32-KB instruction and 32-KB data first-level cache (L1) for each core
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A 256-KB shared instruction/data mid-level (L2) cache for each core
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Up to 20 MB last level cache (LLC): up to 2.5 MB per core instruction/data last level
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cache (LLC), shared among all cores
Supported Technologies:
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Intel Virtualization Technology (Intel
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Intel Virtualization Technology for Directed I/O (Intel
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Intel Virtualization Technology Processor Extensions
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Intel Trusted Execution Technology (Intel
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Intel 64 Architecture
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Intel Streaming SIMD Extensions 4.1 (Intel
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Intel Streaming SIMD Extensions 4.2 (Intel
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Intel Advanced Vector Extensions (Intel
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Intel Hyper-Threading Technology
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Execute Disable Bit
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Intel Turbo Boost Technology
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Intel Intelligent Power Technology
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Enhanced Intel
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3.2.1 Intel
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The Intel QuickPath Interconnect is a high speed, packetized, point-to-point interconnect used
in the processor. The narrow high-speed links stitch together processors in distributed shared
memory and integrated I/O platform architecture. It offers much higher bandwidth with low
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latency. The Intel QuickPath Interconnect has an efficient architecture allowing more
interconnect performance to be achieved in real systems. It has a snoop protocol optimized for
low latency and high scalability, as well as packet and lane structures enabling quick
completions of transactions. Reliability, availability, and serviceability features (RAS) are built into
the architecture.
The physical connectivity of each interconnect link is made up of twenty differential signal pairs
plus a differential forwarded clock. Each port supports a link pair consisting of two uni-directional
links to complete the connection between two components. This supports traffic in both
directions simultaneously. To facilitate flexibility and longevity, the interconnect is defined as
having five layers: Physical, Link, Routing, Transport, and Protocol.
20
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SpeedStep Technology
QuickPath Interconnect
Intel order number G42278-004
Intel® Server Board S2600CO Family TPS
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Hyper-Threading Technology), up to 16 threads
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VT)
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VT-d)
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TXT)
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SSE4.1)
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SSE4.2)
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AVX)
Revision 1.4