Non-Transparent Bridge; Low Pin Count (Lpc) Interface; Universal Serial Bus (Usb) Controller - Intel S2600CO series User Manual

Intel® Server Board S2600CO Family TPS
3.3.1

Non-Transparent Bridge

PCI Express* Non-Transparent Bridge (NTB) acts as a gateway that enables high performance,
low overhead communication between two intelligent subsystems, the local and the remote
subsystems. The NTB allows a local processor to independently configure and control the local
subsystem, provides isolation of the local host memory domain from the remote host memory
domain while enabling status and data exchange between the two domains.
The PCI Express* Port 3A of Intel
can be configured to be a transparent bridge or a NTB with x4/x8 link width and
Gen1/Gen2/Gen3 link speed. Also this NTB port could be attached to another NTB port or PCI
Express* Root Port on another subsystem. NTB supports three 64bit BARs as configuration
space or prefetchable memory windows that can access both 32bit and 64bit address space
through 64bit BARs.
There are three NTB supported configuration:
NTB Port to NTB Port Based Connection (Back-to-Back)

NTB Port to Root Port Based Connection - Symmetric Configuration. The NTB port on

the first system is connected to the root port of the second. The second system's NTB
port is connected to the root port on the first system making this a fully symmetric
configuration.
NTB Port to Root Port Based Connection - Non-Symmetric Configuration. The root port

on the first system is connected to the NTB port of the second system. And it is not
necessary for the first system to be of the Intel
v2 product family.
3.3.2

Low Pin Count (LPC) Interface

The chipset implements an LPC Interface as described in the LPC 1.1 Specification and
provides support for up to two Master/DMI devices. On the server board, the LPC interface is
utilized as an interconnect between the chipset and the Integrated Base Board Management
Controller as well as providing support for the optional Trusted Platform Module (TMP).
3.3.3

Universal Serial Bus (USB) Controller

The chipset has two Enhanced Host Controller Interface (EHCI) host controllers that support
USB high-speed signaling. High-speed USB 2.0 allows data transfers up to 480 Mb/s which is
40 times faster than full-speed USB. The server board utilizes ten USB 2.0 ports from the
chipset. All ports are high-speed, full- speed, and low-speed capable.
Four external USB ports are provided in a stacked housing located on the rear I/O

section of the server board.
Two USB ports are routed to an internal 10-pin connector that can be cabled for front

panel support.
One internal Type 'A' USB port.

One eUSB connector intended for use with an optional eUSB SSD device.

Two USB ports are routed to the Integrated BMC.

Revision 1.4
® ®
Xeon Processor E5-2600 or E5-2600 v2 Product Families
Intel order number G42278-004
Functional Architecture Overview
® ®
Xeon Processor E5-2600 or E5-2600
35