Integrated Memory Controller (Imc) And Memory Subsystem; Figure 12. Integrated Memory Controller Functional Block Diagram - Intel S2600CO series User Manual

Intel® Server Board S2600CO Family TPS
®
The Intel QuickPath Interconnect includes a cache coherency protocol to keep the distributed
memory and caching structures coherent during system operation. It supports both low-latency
source snooping and a scalable home snoop behavior. The coherency protocol provides for
direct cache-to-cache transfers for optimal latency.
3.2.2

Integrated Memory Controller (IMC) and Memory Subsystem

DDR3 MEMORY
2 DIMMs/channel
CHANNEL 3
CHANNEL 2
CHANNEL 1
IOU1
CHANNEL 0
P0

Figure 12. Integrated Memory Controller Functional Block Diagram

Integrated into the processor is a memory controller. Each processor provides four DDR3
channels that support the following:
Unbuffered DDR3 and registered DDR3 DIMMs

LR DIMM (Load Reduced DIMM) for buffered memory solutions demanding higher

capacity memory subsystems
Independent channel mode or lockstep mode

Data burst length of eight cycles for all memory organization modes

Memory DDR3 data transfer rates of 800, 1066, 1333, 1600 and 1866 MT/s

64-bit wide channels plus 8-bits of ECC support for each channel

DDR3 standard I/O Voltage of 1.5 V and DDR3 Low Voltage of 1.35 V

1-Gb, 2-Gb, and 4-Gb DDR3 DRAM technologies supported for these devices:

o UDIMM DDR3 – SR x8 and x16 data widths, DR – x8 data width
o RDIMM DDR3 – SR, DR, and QR – x4 and x8 data widths
o LRDIMM DDR3 – QR – x4 and x8 data widths with direct map or with rank
multiplication
Up to 8 ranks supported per memory channel, 1, 2, or 4 ranks per DIMM

Open with adaptive idle page close timer or closed page policy

Per channel memory test and initialization engine can initialize DRAM to all logical zeros

with valid ECC (with or without data scrambler) or a predefined test pattern
Isochronous access support for Quality of Service (QoS)

Minimum memory configuration: independent channel support with 1 DIMM populated

Integrated dual SMBus* master controllers

Command launch modes of 1n/2n

RAS Support:

o Rank Level Sparing and Device Tagging
Revision 1.4
Intel® Xeon®
E5-2600
CPU 1
IOU2 IOU0
P3 P1 P2
Intel order number G42278-004
Intel® Xeon®
QPI
E5-2600
CPU2
QPI
IOU0
P0 P2
Functional Architecture Overview
DDR3 MEMORY
2 DIMMs/channel
CHANNEL 3
CHANNEL 2
CHANNEL 1
IOU1 IOU2
CHANNEL 0
P3 P1
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