Table of Contents
Advertisement
I
® X
® P
7500 S
NTEL
EON
ROCESSOR
Table 2-20. B_MSR_PMON_EVT_SEL{3-0} Register – Field Definitions
Field
ig
rsv
ig
rsv
ig
pmi_en
ig
ev_sel
en
The B-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry
out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of (2
the U-Box. Upon receipt of the PMI, the U-Box will disable counting (
Counter
Overflow"). During the interval of time between overflow and global disable, the counter value
will wrap and continue to collect events.
In this way, software can capture the precise number of events that occurred between the time uncore
counting was enabled and when it was disabled (or 'frozen') with minimal skew.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-21. B_MSR_PMON_CNT{3-0} Register – Field Definitions
Field
event_count
In addition to generic event counting, each B-Box provides a MATCH/MASK register pair that allow a
user to filter packet traffic (incoming and outgoing) according to the packet Opcode, Message Class and
Physical Address. Various events can be programmed to enable a B-Box performance counter (i.e.
OPCODE_ADDR_IN_MATCH for counter 0) to capture the filter match as an event. The fields are laid out
as follows:
Note:
Refer to
Table 2-103, "Intel® QuickPath Interconnect Packet Message Classes"
Table 2-104, "Opcode Match by Message Class"
Match Register fields.
U
P
G
ERIES
NCORE
ROGRAMMING
UIDE
HW
Bits
Reset
Val
63
0
Read zero; writes ignored. (?)
62:61
0
Reserved; Must write to 0 else behavior is undefined.
60:50
0
Read zero; writes ignored. (?)
50
0
Reserved; Must write to 0 else behavior is undefined.
49:21
0
Read zero; writes ignored. (?)
20
0
When this bit is asserted and the corresponding counter overflows, a PMI
exception is sent to the U-Box.
19:6
0
Read zero; writes ignored. (?)
5:1
0
Select event to be counted.
NOTE: Event selects are NOT symmetric, each counter's event set is
different. See event section and following tables for more details.
0
0
Enable counter
- 1) - N and setting the control register to send a PMI to
48
HW
Bits
Reset
Val
47:0
0
48-bit performance event counter
UNCORE PERFORMANCE MONITORING
Description
Section 2.1.1.1, "Freezing on
Description
to determine the encodings of the B-Box
and
2-32
Advertisement
Table of Contents
