Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual page 124

I ® X ® P 7500 S
NTEL EON ROCESSOR
CYCLES_PGT_STATE
• Title: Time in Page Table State
• Category: Cycle Events
• Event Code: [21:19]0x05 && [7]0x1, Max. Inc/Cyc: 1,
• Definition: Counts cycles page table stays in state as specified in PMU_PGT.opencls_time.
Extension
CLOSED
OPEN
CYCLES_RETRYQ_STARVED
• Title: Time RetryQ Starved
• Category: Cycle Events
• Event Code: [21:19]0x4 && [7]0x1, Max. Inc/Cyc: 1,
• Definition: Counts cycles RetryQ spends in the "starved" state.
CYCLES_RETRYQ_MFULL
• Title: Time RetryQ MFull
• Category: Cycle Events
• Event Code: [21:19]0x3 && [7]0x1, Max. Inc/Cyc: 1,
• Definition: Counts cycles RetryQ spends in the "mfull" state. Also known as the "badly starved" state.
CYCLES_SCHED_MODE
• Title: Time in SCHED_MODE State
• Category: Cycle Events
• Event Code: [21:19]0x01 && [7]0x1, Max. Inc/Cyc: 1,
• Definition: Counts cycles spent in scheduling mode specified in M_CSR_PMU_ISS.sched_mode regis-
ter.
Extension
TRADEOFF
RDPRIO
WRPRIO
ADAPTIVE
DRAM_CMD
• Title: DRAM Commands
• Category: DRAM Commands
• Event Code: 0x0a, Max. Inc/Cyc: 1,
• Definition: Count PLD Related DRAM Events
• NOTE: In order to measure a non-filtered version of the subevents, it is necessary to make sure the
PLD Dep bits [13,7,0] are also set to 0
Extension
ALL
ILLEGAL
PREALL
U P G
ERIES NCORE ROGRAMMING UIDE
Table 2-86. Unit Masks for CYCLES_PGT_STATE
PGT[6]
0x0 Closed Page Mode
0x1 Open Page Mode
Table 2-87. Unit Masks for CYCLES_SCHED_MODE
ISS[6:4]
0x0 Trade-off between read latency/write bandwidth
0x1 Minimize read latency. Reads take priority
0x2 Minimize write latency. Writes take priority
0x3 Adaptive
PLD Dep
Bits
[0]0x0
[12:8]0x0
[12:8]0x1
UNCORE PERFORMANCE MONITORING
Description
Description
ISS Dep
Bits
Advance counter when a DRAM command is detected.
Count Invalid DRAM commands.
Count Preall DRAM commands.
Description
2-112