Special Function Register Definitions; Table 6. Scon1 Special Function Register Definitions - Intel 8XC251SA Hardware Description

Addendum to the 8xc251sa, 8xc251sb, 8xc251sp, 8xc251sq, user’s manual
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3.2

Special Function Register Definitions

The following describes the special function registers associated with the second serial I/O port and their bit
definitions.
3.2.1
SCON1
Address: 9AH
Reset Value: 0000 0000B
Bit
Bit Number
Mnemonic
7
FE1SM0
6
SM1
5
SM2
4
REN1
3
TB8
2
RB8
1
TI1
0
RI1

Table 6. SCON1 Special Function Register Definitions

Framing Error Bit 1:
To Select this function, set the SMOD0 bit in the BGCON register. Set by hard-
ware to indicate an invalid stop bit. Cleared by software, not by valid frames
Second Serial I/O Port Mode Bit 0:
To select this function, clear the SMOD0 bit in the BGCON register. Software
writes to bit SM0 and SM1 to select the second serial I/O port operating
mode. Refer to SM1 bit for mode selections
Second Serial I/O Port Mode Bit 1:
Software write to bit SM0 and SM1 (above) to select the serial port operating
mode.
SM0
SM1
0
0
0
1
1
0
1
1
* Select by programming the SMOD0 bit in the BGCON register
Second Serial I/O Port Mode Bit 2:
Software writes to SM2 enable and disable the multiprocessor communica-
tion and automatic address recognition features. This allows the second
serial I/O port to differentiate between data and command frames and to rec-
ognize slave and broadcast addresses
Receive Enable Bit 1:
To enable reception, set this bit. To enable transmission, clear this bit
Transmit Bit 8:
In modes 2 and 3, software writes the ninth data bit to be transmitted to TB8.
Not used in modes 0 and 1
Receive Bit 8:
Mode 0: not used
Mode 1 (SM2 clear): Set or cleared by hardware to reflect the stop bit
received
Modes 2 and 3 (SM2 set): Set or cleared by hardware to reflect the ninth
data bit received
Second Serial I/O Port Transmit Interrupt Flag Bit:
Set by transmitter after the last data bit is transmitted. Cleared by software
Second Serial I/O Port Receive Interrupt Flag Bit:
Set by the receiver after the last data bit of a frame has been received.
Cleared by software
8xC251Tx Hardware Description
Function
Mode
Description
0
Shift Register
1
8 bit UART
2
9 bit UART
3
9 bit UART
9
Baud Rate
Fosc/12
variable
Fosc/32* or Fosc/64*
variable

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