Table 2-46. R_Msr_Pmon_Ctl{7-0} Event Select; Table 2-47. R_Msr_Pmon_Ctr{15-0} Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
PORT0_IPERF0
PORT0_IPERF1
PORT0_QLX0
PORT0_QLX1
PORT0_XBAR_MM1
PORT0_XBAR_MM2
PORT1_IPERF0
PORT1_IPERF1
PORT1_QLX0
PORT1_QLX1
PORT1_XBAR_MM1
PORT1_XBAR_MM2
PORT2_IPERF0
PORT2_IPERF1
PORT2_QLX0
PORT2_QLX1
PORT2_XBAR_MM1
PORT2_XBAR_MM2
PORT3_IPERF0
PORT3_IPERF1
PORT3_QLX0
PORT3_QLX1
PORT3_XBAR_MM1
PORT3_XBAR_MM2
ILLEGAL
The R-Box performance monitor data registers are 48b wide. A counter overflow occurs when a carry
out bit from bit 47 is detected. Software can force all uncore counting to freeze after N events by
preloading a monitor with a count value of 2
U-Box. Upon receipt of the PMI, the U-Box will disable counting (
Overflow"). During the interval of time between overflow and global disable, the counter value will wrap
and continue to collect events.
In this way, software can capture the precise number of events that occurred between the time uncore
counting was enabled and when it was disabled (or 'frozen') with minimal skew.
If accessible, software can continuously read the data registers without disabling event collection.
Table 2-47. R_MSR_PMON_CTR{15-0} Register – Field Definitions
Field
event_count
U P G
ERIES NCORE ROGRAMMING

Table 2-46. R_MSR_PMON_CTL{7-0} Event Select

Name Code
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
0x16
0x17
0x18-
0x1F
- N and setting the control register to send a PMI to the
48
HW
Bits Reset
Val
47:0 0 48-bit performance event counter
UIDE
Description
Select Event Configured in R_CSR_PORT0_IPERF0
Select Event Configured in R_CSR_PORT0_IPERF1
Select Event Configured in R_CSR_PORT0_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT0_QLX_EVENT_CFG[*1]
Set1 Port0 XBAR Mask/Match
Set2 Port0 XBAR Mask/Match
Select Event Configured in R_CSR_PORT1_IPERF0
Select Event Configured in R_CSR_PORT1_IPERF1
Select Event Configured in R_CSR_PORT1_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT1_QLX_EVENT_CFG[*1]
Set1 Port1 XBAR Mask/Match
Set2 Port1 XBAR Mask/Match
Select Event Configured in R_CSR_PORT2_IPERF0
Select Event Configured in R_CSR_PORT2_IPERF1
Select Event Configured in R_CSR_PORT2_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT2_QLX_EVENT_CFG[*1]
Set1 Port2 XBAR Mask/Match
Set2 Port2 XBAR Mask/Match
Select Event Configured in R_CSR_PORT3_IPERF0
Select Event Configured in R_CSR_PORT3_IPERF1
Select Event Configured in R_CSR_PORT3_QLX_EVENT_CFG[*0]
Select Event Configured in R_CSR_PORT3_QLX_EVENT_CFG[*1]
Set1 Port3 XBAR Mask/Match
Set2 Port3 XBAR Mask/Match
(* illegal selection *)
Section 2.1.1.1, "Freezing on Counter
Description
UNCORE PERFORMANCE MONITORING
2-81