S-Box Pmon State - Counter/Control Pairs + Filters; Table 2-29. S_Msr_Pmon_Ovf_Ctrl Register Fields; Table 2-30. S_Csr_Pmon_Ctl{3-0} Register - Field Definitions - Intel BX80571E7500 - Core 2 Duo 2.93 GHz Processor Programming Manual

I ® X ® P 7500 S
NTEL EON ROCESSOR
Field
clr_ov
2.5.3.3

S-Box PMON state - Counter/Control Pairs + Filters

The following table defines the layout of the S-Box performance monitor control registers. The main
task of these configuration registers is to select the event to be monitored by their respective data
counter. Setting the .ev_sel field performs the event selection. The .en bit must be set to 1 to enable
counting.
Additional control bits include:
- .pmi_en governs what to do if an overflow is detected.
- .threshold - If the .threshold is set to a non-zero value, that value is compared against the incoming
count for that event in each cycle. If the incoming count is >= the threshold value, then the event
count captured in the data register will be incremented by 1.
- .invert - Changes the .threshold test condition to '<'
- .edge_detect - Rather than accumulating the raw count each cycle (for events that can increment by
1 per cycle), the register can capture transitions from no event to an event incoming.
- .reset_occ_cnt - Reset 7b occupancy counter associated with this counter.
Field
ig
rsv
ig
threshold
invert
enable
ig
pmi_en
ig
edge_detect
reset_occ_cnt
ig
umask
ev_sel
U P
ERIES NCORE ROGRAMMING

Table 2-29. S_MSR_PMON_OVF_CTRL Register Fields

HW
Bits Reset
Val
3:0 0 Writing '1' to bit in filed causes corresponding bit in 'Overflow PerfMon
Counter' field in S_CSR_PMON_GLOBAL_STATUS register to be cleared to
0.
Table 2-30. S_CSR_PMON_CTL{3-0} Register – Field Definitions
HW
Bits Reset
Val
63 0 Read zero; writes ignored. (?)
62:61 0 Reserved; Must write to 0 else behavior is undefined.
60:32 0 Read zero; writes ignored. (?)
31:24 0 Threshold used for counter comparison.
23 0 Invert threshold comparison. When '0', the comparison will be thresh >=
event. When '1', the comparison will be threshold < event.
22 0 Enable counter.
21 0 Read zero; writes ignored. (?)
20 0 PMI Enable. If bit is set, when corresponding counter overflows, a PMI
exception is sent to the U-Box.w
19 0 Read zero; writes ignored. (?)
18 0 Edge Detect. When bit is set, 0->1 transition of a one bit event input will
cause counter to increment. When bit is 0, counter will increment for
however long event is asserted.
17 0 Reset Occupancy Counter associated with this counter.
16 0 Read zero; writes ignored. (?)
15:8 0 Unit Mask - select subevent of event.
7:0 0 Event Select
G
UIDE
Description
Description
UNCORE PERFORMANCE MONITORING
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