Texas Instruments TMS320C67X Reference Manual page 302

STH
Store Halfword to Memory With a 5-Bit Unsigned Constant Offset or Register Offset
Example 2
Before
instruction
A1
9A32 2634h
A10 0000 0100h
A11 0000 0004h
mem F8h
mem 100h
3-242 Instruction Set
STH .D1 A1,*A10−−[A11]
A1
A10
A11
0000h mem F8h
0000 mem 100h
1 cycle after
instruction
9A32 2634h
0000 00F8h
0000 0004h
0000h mem F8h
0000h mem 100h
3 cycles after
instruction
A1 9A32 2634h
A10 0000 00F8h
A11 0000 0004h
0000h
2634h
SPRU733