Fully Serial P-Bit Pattern In A Fetch Packet; Fully Parallel P-Bit Pattern In A Fetch Packet - Texas Instruments TMS320C67X Reference Manual

Example 3−1. Fully Serial p-Bit Pattern in a Fetch Packet
31 0 31
0
Instruction Instruction
A B
Example 3−2. Fully Parallel p-Bit Pattern in a Fetch Packet
31 0 31
1
Instruction Instruction
A B
Cycle/Execute
Packet
1 A
SPRU733
This p-bit pattern:
0 31 0 31
0 0
Instruction Instruction
C D
results in this execution sequence:
Cycle/Execute
Packet Instructions
1
2
3
4
5
6
7
8
The eight instructions are executed sequentially.
This p-bit pattern:
0 31 0 31
1 1
Instruction Instruction
C D
results in this execution sequence:
B C
All eight instructions are executed in parallel.
0 31 0 31
0 0
Instruction Instruction
E F
A
B
C
D
E
F
G
H
0 31 0 31
1 1
Instruction Instruction
E F
Instructions
D E F
Parallel Operations
0 31 0 31
0 0
Instruction Instruction
G H
0 31 0 31
1 1
Instruction Instruction
G H
G H
Instruction Set
0
0
0
0
3-17